Can Livanelioglu

Orcid: 0000-0001-7123-5761

According to our database1, Can Livanelioglu authored at least 7 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
19.10 A 4.6GHz 63.3fs<sub>rms</sub> PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving -255.2dB FoM<sub>J</sub> Including the XO Power and Noise.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

A 3.47 NEF 175.2dB FOMs Direct Digitization Front-End Featuring Delta Amplification for Enhanced Dynamic Range and Energy Efficiency in Bio-Signal Acquisition.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024
An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance.
IEEE J. Solid State Circuits, April, 2024

2023
A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

An Energy-Efficient Impedance-Boosted Discrete-Time Amplifier Achieving 0.34 Noise Efficiency Factor and 389 MΩ Input Impedance.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A 0.0014 mm<sup>2</sup>, 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface Circuits.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Ultra-Low-Power FDSOI Neural Circuits for Extreme-Edge Neuromorphic Intelligence.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021


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