Jiang Gong

According to our database, Jiang Gong authored at least 11 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Cryo-CMOS PLL for Quantum Computing Applications.

Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie

IEEE J. Solid State Circuits, May, 2023

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit.

Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie

IEEE J. Solid State Circuits, 2023

2022

A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications.

Jiang Gong, Yue Chen, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Low-Jitter and Low-Spur Charge-Sampling PLL.

Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie

IEEE J. Solid State Circuits, 2022

A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and _pp Supply Ripple.

Yue Chen, Jiang Gong, Robert Bogdan Staszewski, Masoud Babaie

IEEE J. Solid State Circuits, 2022

A 3V 15b 157μW Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing.

Luc Enthoven, Job van Staveren, Jiang Gong, Masoud Babaie, Fabio Sebastiano

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FoM_A in 22nm FinFET.

Jiang Gong, Bishnu Patra, Luc Enthoven, Job van Staveren, Fabio Sebastiano, Masoud Babaie

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs.

Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021

A 2.7mW 45fsrms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications.

Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

19.3 A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications.

Jiang Gong, Yue Chen, Fabio Sebastiano, Edoardo Charbon, Masoud Babaie

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers.

Mohammadreza Mehrpoo, Bishnu Patra, Jiang Gong, Pascal Alexander 't Hart, Jeroen P. G. van Dijk, Harald Homulle, Gerd Kiene, Andrei Vladimirescu, Fabio Sebastiano, Edoardo Charbon, Masoud Babaie

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019