Sina Arjmandpour

According to our database, Sina Arjmandpour authored at least 10 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

An R-RC Oscillator Achieving Second-Order Temperature Compensation and Oscillating Independently From the Comparator and Reset Delays.

Youngwoo Ji, Jiawei Liao, Sina Arjmandpour, Alessandro Novello, Jae-Yoon Sim, Taekwang Jang

IEEE J. Solid State Circuits, March, 2026

Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond.

Paul Scheffler, Thomas Benz, Tim Fischer, Lorenzo Leone, Sina Arjmandpour, Luca Benini

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

An 11bit, 140fs resolution, and 683fs INL Zero-Slope Digital-to-Time Converter for Fractional Frequency Syntheses.

Kyeongwon Jeong, Hesam Omdeh Ghiasi, Seungki Hong, Sina Arjmandpour, Oscar Toomey, Taekwang Jang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

A 4.6-GHz 54.5-fs_rms PLL-XO Co-Design Featuring a Pulse-Injection XO Driver.

Can Livanelioglu, Long He, Jiang Gong, Sina Arjmandpour, Gabriele Atzeni, Taekwang Jang

IEEE J. Solid State Circuits, December, 2025

19.10 A 4.6GHz 63.3fs_rms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving -255.2dB FoM_J Including the XO Power and Noise.

Can Livanelioglu, Long He, Jiang Gong, Sina Arjmandpour, Gabriele Atzeni, Taekwang Jang

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance.

Gabriele Atzeni, Can Livanelioglu, Sina Arjmandpour, Taekwang Jang

IEEE J. Solid State Circuits, April, 2024

A 0.29pJ/Step Fully Discrete-Time Charge Domain Bridge-to-Digital Converter for Force Sensing in Spinal Implants Using RC Bridge.

Tim Keller, Rosario M. Incandela, Xi Chen, Hesam Ghiasi, Mohsen Khodaee, Sina Arjmandpour, Jiawei Liao, H. Long, Tobias Götschi, Jonas Widmer, Taekwang Jang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing.

Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, SeongHwan Cho, Taekwang Jang

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

An Energy-Efficient Impedance-Boosted Discrete-Time Amplifier Achieving 0.34 Noise Efficiency Factor and 389 MΩ Input Impedance.

Gabriele Atzeni, Can Livanelioglu, Lavinia Recchioni, Sina Arjmandpour, Taekwang Jang

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

A Second-Order Temperature-Compensated On-Chip R-RC Oscillator Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range.

Youngwoo Ji, Jiawei Liao, Sina Arjmandpour, Alessandro Novello, Jae-Yoon Sim, Taekwang Jang

Proceedings of the IEEE International Solid-State Circuits Conference, 2022