Can Wang

Orcid: 0000-0002-6175-5445

Affiliations:
  • Stanford University, CA, USA
  • Hong Kong University of Science and Technology, HKUST, Optical Wireless Laboratory, IC Design Center, Department of Electronic and Computer Engineering, Kowloon, Hong Kong
  • Fudan University, PhotonIC Technologies, State Key Laboratory of ASIC and System, Shanghai, China (2017)


According to our database1, Can Wang authored at least 8 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR.
IEEE J. Solid State Circuits, February, 2024

2021
Sensing and Cancellation Circuits for Mitigating EMI-Related Common Mode Noise in High-Speed PAM-4 Transmitter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects.
IEEE Open J. Circuits Syst., 2021

2020
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator.
IEEE J. Solid State Circuits, 2020

A Real-Time RGB PAM-4 Visible Light Communication System Based on a Transceiver Design with Pre- and Post-equalizations.
Proceedings of the Machine Learning and Intelligent Communications, 2020

2019
A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 GHZ in 65-NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


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