Li Wang

Orcid: 0000-0003-3937-8273

Affiliations:
  • Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Hong Kong


According to our database1, Li Wang authored at least 18 papers between 2019 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
A 48-Gb/s Inductorless PAM-4 Optical Receiver With 1.28-pJ/bit Efficiency in 28-nm CMOS.
IEEE J. Solid State Circuits, May, 2026

2025
A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS.
IEEE J. Solid State Circuits, November, 2025

A 0.32-pJ/b 100-Gb/s PAM-4 TIA in 28-nm CMOS.
IEEE Solid State Circuits Lett., 2025

2024
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR.
IEEE J. Solid State Circuits, February, 2024

A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm<sup>2</sup> area in 28-nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023
A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2021
Sensing and Cancellation Circuits for Mitigating EMI-Related Common Mode Noise in High-Speed PAM-4 Transmitter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects.
IEEE Open J. Circuits Syst., 2021

A W-Band Single-Antenna FMCW Radar Transceiver With Adaptive Leakage Cancellation.
IEEE J. Solid State Circuits, 2021

A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator.
IEEE J. Solid State Circuits, 2020

An RGB-LED Driver with Feed-Forward Equalization Used for PAM-4 Visible Light Communication.
Proceedings of the Machine Learning and Intelligent Communications, 2020

A Real-Time RGB PAM-4 Visible Light Communication System Based on a Transceiver Design with Pre- and Post-equalizations.
Proceedings of the Machine Learning and Intelligent Communications, 2020

2019
Smart Table Applications Based on Magnetic Resonance Wireless Power Transfer.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Design of a Real-Time Visible Laser Light Communication System with Basedband in FPGA for High Definition video Transmission.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

A Dual-Resonance Matching Circuit for Magnetic Resonance Wireless Power Transfer Systems.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019


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