Cewen Liu

According to our database, Cewen Liu authored at least 9 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A high speed and reflection cancel adaptive equalization using 4-tap floating FFE and 2-tap speculative pre-decision and loop-refactored DFE for wireline receiver.

Xiaoyue Hu, Fangxu Lv, Jin Zhang, Jiaqing Xu, Qiang Wang, Cewen Liu, Chaolong Xu, Zhouhao Yang, Jinwen Li

Microelectron. J., 2026

2025

An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver.

Mingche Lai, Chaolong Xu, Fangxu Lv, Jiaqing Xu, Qiang Wang, Yang Ou, Xiaoyue Hu, Cewen Liu, Zhouhao Yang

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025

An Efficient Point Spread Function Inversion Method for Image-Domain One-Way Wave-Equation Least-Squares Migration.

Cewen Liu, Mengyao Sun, Wei Wu, Nanxun Dai, Mingjie Guo, Haohuan Fu

IEEE Trans. Geosci. Remote. Sens., 2025

A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver.

Cewen Liu, Xingyun Qi, Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai

Microelectron. J., 2025

Enhancing 3D migration images resolution: A fast and robust implicit point spread function deconvolution method based on wavenumber domain representation.

Zhongfan Jia, Cewen Liu, Haohuan Fu, Kaisheng Ma

Comput. Geosci., 2025

Deep Learning-Based Rapid Fire Detection in Buildings Using Acoustic Wave Travel Time Information.

Mengyao Sun, Cewen Liu

IEEE Access, 2025

Real-Time Demonstration of FPGA-Based Advanced Equalizer with ZF-NL-RSSE for Data Center Interconnects.

Zhouhao Yang, Fangxu Lv, Mingche Lai, Zhang Luo, Weixia Xu, Chaolong Xu, Kefan Ma, Xiaoyue Hu, Cewen Liu, Zheng Peng, Xianchao Zeng

Proceedings of the European Conference on Optical Communications, 2025

2024

A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE.

Xiaoyue Hu, Fangxu Lv, Mingche Lai, Zhang Luo, Qiang Wang, Chaolong Xu, Ruotian Yin, Zhouhao Yang, Cewen Liu

IEICE Electron. Express, 2024

A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver.

Chaolong Xu, Fangxu Lv, Mingche Lai, Zhang Luo, Xingyun Qi, Jiaqing Xu, Qiang Wang, Liquan Xiao, Cewen Liu, Hua Xu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024