Fangxu Lv

Orcid: 0000-0001-8301-0359

According to our database1, Fangxu Lv authored at least 22 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023
A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology.
Microelectron. J., October, 2023

Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications.
Proceedings of the 4th International Conference on Computer Engineering and Intelligent Control, 2023

2022
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.
Microelectron. J., 2022

2021
An Adaptive Equalization Algorithm for High Speed SerDes.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators.
IEEE J. Solid State Circuits, 2020

A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020

A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology.
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

2019
A 4-40 Gb/s PAM-4 transmitter with a hybrid driver in 65 nm CMOS technology.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications.
Microelectron. J., 2018

2017
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS.
IEEE J. Solid State Circuits, 2017

A 40-80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Compressive Spectrum Sensing Based on Sparse Sub-band Basis in Wireless Sensor Network.
Proceedings of the Advances in Wireless Sensor Networks - The 8th China Conference, 2014


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