Weixia Xu

Orcid: 0000-0003-2412-6591

According to our database1, Weixia Xu authored at least 71 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
M-LSM: An Improved Multi-Liquid State Machine for Event-Based Vision Recognition.
J. Comput. Sci. Technol., December, 2023

Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISA.
IEEE Trans. Parallel Distributed Syst., November, 2023

Latent feature reconstruction for unsupervised anomaly detection.
Appl. Intell., October, 2023

Path-Based Multicast Routing for Network-on-Chip of the Neuromorphic Processor.
J. Comput. Sci. Technol., September, 2023

SSD-SGD: Communication Sparsification for Distributed Deep Learning Training.
ACM Trans. Archit. Code Optim., March, 2023

Molecular Property Prediction Based on Graph Structure Learning.
CoRR, 2023

CWA-LSTM: A Stock Price Prediction Model Based on Causal Weight Adjustment.
Proceedings of the Advanced Intelligent Computing Technology and Applications, 2023

2022
Lotus: a memory organization for loose and tight coupling neurons in neuromorphic architecture.
CCF Trans. High Perform. Comput., December, 2022

LSMCore: A 69k-Synapse/mm<sup>2</sup> Single-Core Digital Neuromorphic Processor for Liquid State Machine.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Hardware-aware liquid state machine generation for 2D/3D Network-on-Chip platforms.
J. Syst. Archit., 2022

Large-scale full-programmable quantum walk and its applications.
CoRR, 2022

Revisiting network congestion avoidance through adaptive packet-chaining reservation.
Comput. Networks, 2022

Stride Equality Prediction for Value Speculation.
IEEE Comput. Archit. Lett., 2022

Identifying essential proteins from protein-protein interaction networks based on influence maximization.
BMC Bioinform., 2022

Unicorn: a multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neurons.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Universal consistency of twin support vector machines.
Int. J. Mach. Learn. Cybern., 2021

A multi-objective LSM/NoC architecture co-design framework.
J. Syst. Archit., 2021

HashHeat: A hashing-based spatiotemporal filter for dynamic vision sensor.
Integr., 2021

A neural architecture search based framework for liquid state machine design.
Neurocomputing, 2021

Evolutionary Recurrent Neural Architecture Search.
IEEE Embed. Syst. Lett., 2021

Protein-protein interaction prediction based on ordinal regression and recurrent convolutional neural networks.
BMC Bioinform., 2021

Advanced Architecture Design of High-Radix Router Based on Chiplet Integration and IP Reusability.
Proceedings of the 2021 IEEE 23rd Int Conf on High Performance Computing & Communications; 7th Int Conf on Data Science & Systems; 19th Int Conf on Smart City; 7th Int Conf on Dependability in Sensor, 2021

2020
A Natural-language-based Visual Query Approach of Uncertain Human Trajectories.
IEEE Trans. Vis. Comput. Graph., 2020

A Memristor-Based Spiking Neural Network With High Scalability and Learning Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

OD-SGD: One-Step Delay Stochastic Gradient Descent for Distributed Training.
ACM Trans. Archit. Code Optim., 2020

ASIE: An Asynchronous SNN Inference Engine for AER Events Processing.
ACM J. Emerg. Technol. Comput. Syst., 2020

SIES: A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array.
J. Comput. Sci. Technol., 2020

ssd-sgd: communication sparsification for distributed deep learning training.
CoRR, 2020

SeqXFilter: A Memory-efficient Denoising Filter for Dynamic Vision Sensors.
CoRR, 2020

OD-SGD: One-step Delay Stochastic Gradient Descent for Distributed Training.
CoRR, 2020

A Neural Architecture Search based Framework for Liquid State Machine Design.
CoRR, 2020

A Noise Filter for Dynamic Vision Sensors based on Global Space and Time Information.
CoRR, 2020

Exploration of Input Patterns for Enhancing the Performance of Liquid State Machines.
CoRR, 2020

CompressedCache: Enabling Storage Compression on Neuromorphic Processor for Liquid State Machine.
Proceedings of the Network and Parallel Computing, 2020

Design of Converged Network Coding Layer for the Ethernet and HPC High-Speed Network.
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020

SNEAP: A Fast and Efficient Toolchain for Mapping Large-Scale Spiking Neural Network onto NoC-based Neuromorphic Platform.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Application-specific network-on-chip design space exploration framework for neuromorphic processor.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

HashHeat: An O(C) Complexity Hashing-based Filter for Dynamic Vision Sensor.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Liquid State Machine Applications Mapping for NoC-Based Neuromorphic Platforms.
Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

2019
SketchDLC: A Sketch on Distributed Deep Learning Communication via Trace Capturing.
ACM Trans. Archit. Code Optim., 2019

Statistical learning with group invariance: problem, method and consistency.
Int. J. Mach. Learn. Cybern., 2019

PRTSM: Hardware Data Arrangement Mechanisms for Convolutional Layer Computation on the Systolic Array.
Proceedings of the Network and Parallel Computing, 2019

2018
A Power Efficient Hardware Implementation of the IF Neuron Model.
Proceedings of the Advanced Computer Architecture - 12th Conference, 2018

2017
Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Heterogeneous acceleration for CNN training with many integrated core.
Proceedings of the 2017 IEEE International Conference on Signal Processing, 2017

2016
Monaural Speech Separation on Many Integrated Core Architecture.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture.
Proceedings of the Computer Engineering and Technology - 20th CCF Conference, 2016

Graphein: A Novel Optical High-Radix Switch Architecture for 3D Integration.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

2015
A low-latency fine-grained dynamic shared cache management scheme for chip multi-processor.
Proceedings of the 34th IEEE International Performance Computing and Communications Conference, 2015

2014
An incentive compatible reputation mechanism for P2P systems.
J. Supercomput., 2014

Hybrid hierarchy storage system in MilkyWay-2 supercomputer.
Frontiers Comput. Sci., 2014

Low-latency last-level cache structure based on grouped cores in Chip Multi-Processor.
Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

Fast NIC based RDMA implementation for adaptive unreliable networks.
Proceedings of the 11th IEEE/ACS International Conference on Computer Systems and Applications, 2014

2013
Scalable NIC Architecture to Support Offloading of Large Scale MPI Barrier.
Proceedings of the Advanced Parallel Processing Technologies, 2013

2012
State space reduction in modeling checking parameterized cache coherence protocol by two-dimensional abstraction.
J. Supercomput., 2012

Distributed Coverage in Wireless Ad Hoc and Sensor Networks by Topological Graph Approaches.
IEEE Trans. Computers, 2012

Frame Error Rate Testing for High Speed Optical Interconnect.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2012

Optimizing Private Memory Performance by Dynamically Deactivating Cache Coherence.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

PIM: A Policy-Based Incentive Mechanism for Promoting Honest Recommendations in Reputation Systems.
Proceedings of the 12th IEEE International Conference on Computer and Information Technology, 2012

2011
Optimizing Linpack Benchmark on GPU-Accelerated Petascale Supercomputer.
J. Comput. Sci. Technol., 2011

Extracting minimal unsatisfiable subformulas in satisfiability modulo theories.
Comput. Sci. Inf. Syst., 2011

A Formalization of an Emulation Based Co-designed Virtual Machine.
Proceedings of the Fifth International Conference on Innovative Mobile and Internet Services in Ubiquitous Computing, 2011

Finding First-Order Minimal Unsatisfiable Cores with a Heuristic Depth-First-Search Algorithm.
Proceedings of the Intelligent Data Engineering and Automated Learning - IDEAL 2011, 2011

A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A Parallel Processing Scheme for Large-Size Sliding-Window Applications.
Proceedings of the 13th IEEE International Conference on High Performance Computing & Communication, 2011

2010
Exploiting Loop-Carried Stream Reuse for Scientific Computing Applications on the Stream Processor.
Int. J. Commun. Netw. Syst. Sci., 2010

TH-1: China's first petaflop supercomputer.
Frontiers Comput. Sci. China, 2010

A Novel Chaining Approach for Direct Control Transfer Instructions.
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

2009
An efficient stream memory architecture for heterogeneous multicore processor.
Proceedings of the 14th IEEE Symposium on Computers and Communications (ISCC 2009), 2009

DTM: Decoupled Hardware Transactional Memory to Support Unbounded Transaction and Operating System.
Proceedings of the ICPP 2009, 2009

1997
A Dual-Processors Multithreaded Architecture and Its Driven Execution Model.
Proceedings of the 1997 Advances in Parallel and Distributed Computing Conference (APDC '97), 1997


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