Chang Yun Park

Orcid: 0000-0001-8334-7402

According to our database1, Chang Yun Park authored at least 21 papers between 1991 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Developing an asynchronous NoAck-based full-duplex MAC for IEEE 802.11 networks in a systems approach.
Comput. Commun., 2021

2018
A Responsible Airtime Approach for True Time-Based Fairness in Multi-Rate WiFi Networks.
Sensors, 2018

2014
Adjusting the Retry Limit for Congestion Control in an Overlapping Private BSS Environment.
KSII Trans. Internet Inf. Syst., 2014

2012
Improving Performance of Remote TCP in Cognitive Radio Networks.
KSII Trans. Internet Inf. Syst., 2012

2011
A Practical Unacknowledged Unicast Transmission in IEEE 802.11 Networks.
KSII Trans. Internet Inf. Syst., 2011

Mobility-Aware Interference Avoidance Scheme for Vehicular WLANs.
KSII Trans. Internet Inf. Syst., 2011

2007
Selective code transformation for dual instruction set processors.
ACM Trans. Embed. Comput. Syst., 2007

2005
Experiments on the Energy Saving and Performance Effects of IEEE 802.11 Power Saving Mode (PSM).
Proceedings of the Information Networking, 2005

2004
A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

2003
A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors.
Proceedings of the 3rd International Workshop on Worst-Case Execution Time Analysis, 2003

2001
Bounding Cache-Related Preemption Delay for Real-Time Systems.
IEEE Trans. Software Eng., 2001

1998
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling.
IEEE Trans. Computers, 1998

1997
Threaded Prefetching: A New Instruction Memory Hierarchy for Real-Time Systems.
Real Time Syst., 1997

Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling.
Proceedings of the 18th IEEE Real-Time Systems Symposium (RTSS '97), 1997

1996
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling.
Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), 1996

1995
An Accurate Worst Case Timing Analysis for RISC Processors.
IEEE Trans. Software Eng., 1995

Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study.
Proceedings of the 16th IEEE Real-Time Systems Symposium, 1995

1994
An Accurate Worst Case Timing Analysis Technique for RISC Processors.
Proceedings of the 15th IEEE Real-Time Systems Symposium (RTSS '94), 1994

1993
Predicting Program Execution Times by Analyzing Static and Dynamic Program Paths.
Real Time Syst., 1993

A Dual-Mode Instruction Prefetch Scheme for Improved Worst Case and Average Case Program Execution Times.
Proceedings of the Real-Time Systems Symposium. Raleigh-Durham, NC, USA, December 1993, 1993

1991
Experiments with a Program Timing Tool Based on Source-Level Timing Schema.
Computer, 1991


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