Chong-Sang Kim

According to our database1, Chong-Sang Kim authored at least 27 papers between 1993 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




An accurate and practical buffer allocation model for the buffer cache based on marginal gains.
Inf. Process. Lett., 2003

Bounding Cache-Related Preemption Delay for Real-Time Systems.
IEEE Trans. Software Eng., 2001

LRFU: A Spectrum of Policies that Subsumes the Least Recently Used and Least Frequently Used Policies.
IEEE Trans. Computers, 2001

A predictive call admission control scheme for low Earth orbit satellite networks.
IEEE Trans. Veh. Technol., 2000

A Low-Overhead, High-Performance Unified Buffer Management Scheme That Exploits Sequential and Looping References.
Proceedings of the 4th Symposium on Operating System Design and Implementation (OSDI 2000), 2000

Cache-Conscious Limited Preemptive Scheduling.
Real Time Syst., 1999

On the Existence of a Spectrum of Policies that Subsumes the Least Recently Used (LRU) and Least Frequently Used (LFU) Policies.
Proceedings of the 1999 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, 1999

Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling.
IEEE Trans. Computers, 1998

U-cache: A cost-effective solution to the virtual cache synonym problem.
Microprocess. Microsystems, 1998

Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems.
Proceedings of the Languages, 1998

Threaded Prefetching: A New Instruction Memory Hierarchy for Real-Time Systems.
Real Time Syst., 1997

Cache performance improvement through on-demand, in-cache page clearing.
Microprocess. Microsystems, 1997

Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling.
Proceedings of the 18th IEEE Real-Time Systems Symposium (RTSS '97), 1997

The Design and Performance Evaluation of the RAID 5 Controller using the Load-Balanced Destage Algorithm.
Proceedings of the 1997 International Conference on Parallel and Distributed Systems (ICPADS '97), 1997

Analysis of cache-related preemption delay in fixed-priority preemptive scheduling.
Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), 1996

Efficiently supporting hard/soft deadline transactions in real-time database systems.
Proceedings of the Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30, 1996

An Accurate Worst Case Timing Analysis for RISC Processors.
IEEE Trans. Software Eng., 1995

Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study.
Proceedings of the 16th IEEE Real-Time Systems Symposium, 1995

U-Cache: A Cost-Effective Solution to the Synonym Problem.
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

Competitive learning neural network with dynamic output neuron generation.
Neural Parallel Sci. Comput., 1994

A worst case timing analysis technique for instruction prefetch buffers.
Microprocess. Microprogramming, 1994

An Accurate Worst Case Timing Analysis Technique for RISC Processors.
Proceedings of the 15th IEEE Real-Time Systems Symposium (RTSS '94), 1994

Multiple neural networks using the reduced input dimension.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

V-P cache: a storage efficient virtual cache organization.
Microprocess. Microsystems, 1993

Threaded prefetching: An adaptive instruction prefetch mechanism.
Microprocess. Microprogramming, 1993

Caller ID System in the Internet Environment.
Proceedings of the 4th USENIX Security Symposium, Santa Clara, CA, USA, October 4-6, 1993, 1993

A Dual-Mode Instruction Prefetch Scheme for Improved Worst Case and Average Case Program Execution Times.
Proceedings of the Real-Time Systems Symposium. Raleigh-Durham, NC, USA, December 1993, 1993