Sheayun Lee

According to our database, Sheayun Lee authored at least 13 papers between 1998 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Fall Detection using Biometric Information Based on Multi-Horizon Forecasting.

Inkyung Kim, Daehee Kim, Sunyoung Kwon, Sheayun Lee, Jaekoo Lee

Proceedings of the 26th International Conference on Pattern Recognition, 2022

2018

HIL: A Framework for Compositional FTL Development and Provably-Correct Crash Recovery.

Jin-Yong Choi, Eyee Hyun Nam, Yoon Jae Seong, Jinhyuk Yoon, Sookwan Lee, Hongseok Kim, Jeongsu Park, Yeong-Jae Woo, Sheayun Lee, Sang Lyul Min

ACM Trans. Storage, 2018

FMMU: a hardware-accelerated flash map management unit for scalable performance of flash-based SSDs.

Yeong-Jae Woo, Sheayun Lee, Sang Lyul Min

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

P-BMS: A Bad Block Management Scheme in Parallelized Flash Memory Storage Devices.

Hongseok Kim, Eyee Hyun Nam, JiHyuck Yun, Sheayun Lee, Sang Lyul Min

ACM Trans. Embed. Comput. Syst., 2017

2008

A design framework for real-time embedded systems with code size and energy constraints.

Sheayun Lee, Insik Shin, Woonseok Kim, Insup Lee, Sang Lyul Min

ACM Trans. Embed. Comput. Syst., 2008

2007

Selective code transformation for dual instruction set processors.

Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min

ACM Trans. Embed. Comput. Syst., 2007

2006

Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study.

Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2004

A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor.

Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min

Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

2003

A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors.

Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min

Proceedings of the 3rd International Workshop on Worst-Case Execution Time Analysis, 2003

Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation.

Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson

Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

2001

An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors.

Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang

Proceedings of The Workshop on Languages, 2001

1999

Cache-Conscious Limited Preemptive Scheduling.

Sheayun Lee, Sang Lyul Min, Chong-Sang Kim, Chang-Gun Lee, Minsuk Lee

Real Time Syst., 1999

1998

Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems.

Sheayun Lee, Chang-Gun Lee, Minsuk Lee, Sang Lyul Min, Chong-Sang Kim

Proceedings of the Languages, 1998