Jaejin Lee
Orcid: 0000-0003-4638-8170
According to our database1,
Jaejin Lee
authored at least 145 papers
between 1995 and 2024.
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Bibliography
2024
Attention-based Reinforcement Learning for Combinatorial Optimization: Application to Job Shop Scheduling Problem.
CoRR, 2024
2023
Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access Memory.
IEEE Access, 2023
Improving Bit-Error-Rate Performance Using Modulation Coding Techniques for Spin-Torque Transfer Magnetic Random Access Memory.
IEEE Access, 2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the 30th IEEE International Conference on High Performance Computing, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
SIRTEM: Spatially Informed Rapid Testing for Epidemic Modeling and Response to COVID-19.
ACM Trans. Spatial Algorithms Syst., 2022
IEEE Trans. Parallel Distributed Syst., 2022
Parallel Detection Based on a Generalized Partial Response Target for Staggered Bit-Patterned Media Recording Systems.
IEEE Access, 2022
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022
2021
IEEE Access, 2021
Proceedings of the PLDI '21: 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the HPDC '21: The 30th International Symposium on High-Performance Parallel and Distributed Computing, 2021
2020
ACM Trans. Parallel Comput., 2020
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.
IEEE J. Solid State Circuits, 2020
IET Commun., 2020
CyCNN: A Rotation Invariant CNN using Polar Mapping and Cylindrical Convolution Layers.
CoRR, 2020
Proceedings of the PPoPP '20: 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2020
Compiler-directed soft error resilience for lightweight GPU register file protection.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
2019
ACM Trans. Parallel Comput., 2019
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019
Proceedings of the IEEE International Symposium on Workload Characterization, 2019
Proceedings of the 33rd International Conference on Information Networking, 2019
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
2018
IEEE Trans. Parallel Distributed Syst., 2018
Measurement and Analysis of Electric Signal Transmission Using Human Body as Medium for WBAN Applications.
IEEE Trans. Instrum. Meas., 2018
Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2018
Interpixel interference mitigation using differential coding in vehicular visible light communication based image sensor.
Proceedings of the 2018 International Conference on Information Networking, 2018
2017
Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2017
Proceedings of the Languages and Compilers for Parallel Computing, 2017
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017
2016
What We Can Learn from the Data: A Multiple-Case Study Examining Behavior Patterns by Students with Different Characteristics in Using a Serious Game.
Technol. Knowl. Learn., 2016
Elimination of two-dimensional intersymbol interference through the use of a 9/12 two-dimensional modulation code.
IET Commun., 2016
Translating OpenMP device constructs to OpenCL using unnecessary data transfer elimination.
Proceedings of the International Conference for High Performance Computing, 2016
Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International Conference on Information and Communication Technology Convergence, 2016
Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016
2015
IEEE Trans. Parallel Distributed Syst., 2015
IEEE Trans. Parallel Distributed Syst., 2015
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits.
IEEE J. Solid State Circuits, 2015
Proceedings of the International Conference for High Performance Computing, 2015
Proceedings of the Job Scheduling Strategies for Parallel Processing, 2015
Proceedings of the Seventh International Conference on Ubiquitous and Future Networks, 2015
Proceedings of the 2015 International Conference on Information Networking, 2015
Proceedings of the 2015 International Conference on Information Networking, 2015
Improving SOVA output using extrinsic informations for bit patterned media recording.
Proceedings of the IEEE International Conference on Consumer Electronics, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM.
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 Workshop on Programming models for SIMD/Vector processing, 2014
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
23Gbps 9.4pJ/bit 80/100GHz band CMOS transceiver with on-board antenna for short-range communication.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
Proceedings of the International Conference on Computing, Networking and Communications, 2013
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
ACM Trans. Archit. Code Optim., 2012
Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2012
Proceedings of the 31st IEEE Military Communications Conference, 2012
Proceedings of the International Conference on Supercomputing, 2012
An automatic code overlaying technique for multicores with explicitly-managed memory hierarchies.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012
2011
ACM Trans. Embed. Comput. Syst., 2011
Coupling canceller maximum-likelihood (CCML) detection for multi-level cell NAND flash memory.
IEEE Trans. Consumer Electron., 2011
Comput. Educ., 2011
Proceedings of the 7th International Conference on Virtual Execution Environments, 2011
Proceedings of the 16th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2011
An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures.
Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, 2011
Proceedings of the Languages and Compilers for Parallel Computing, 2011
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Proceedings of the APSys '11 Asia Pacific Workshop on Systems, 2011
SFMalloc: A Lock-Free and Mostly Synchronization-Free Dynamic Memory Allocator for Manycores.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
IEEE Trans. Computers, 2010
IEEE Trans. Computers, 2010
J. Parallel Distributed Comput., 2010
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
Proceedings of the 10th International conference on Embedded software, 2010
A software-SVM-based transactional memory for multicore accelerator architectures with local memory.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
IEEE Trans. Parallel Distributed Syst., 2009
High recording density hard disk channel equalization using a bilinear recursive polynomial model.
IEICE Electron. Express, 2009
Design and implementation of software-managed caches for multicores with local memory.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
2008
ACM Trans. Embed. Comput. Syst., 2008
Message-passing iterative decoding between detector and RSC code decoder for PMR channel.
IEEE Trans. Consumer Electron., 2008
J. Comput. Sci. Eng., 2008
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008
Proceedings of the 8th ACM & IEEE International conference on Embedded software, 2008
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008
2007
ACM Trans. Embed. Comput. Syst., 2007
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007
2006
J. Algorithms, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006
A dynamic code placement technique for scratchpad memory using postpass optimization.
Proceedings of the 2006 International Conference on Compilers, 2006
2005
IEEE Trans. Consumer Electron., 2005
IEEE Trans. Computers, 2005
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2005
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2005
Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-Aware Compiler.
Proceedings of the Languages and Compilers for Parallel Computing, 2005
2004
A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004
Proceedings of the EMSOFT 2004, 2004
2003
IEEE Trans. Parallel Distributed Syst., 2003
A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors.
Proceedings of the 3rd International Workshop on Worst-Case Execution Time Analysis, 2003
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003
Proceedings of the 17th Annual International Conference on Supercomputing, 2003
Proceedings of the Grid and Cooperative Computing, Second International Workshop, 2003
2002
Modified maximum a posteriori decoding algorithm using a priori probability ratio as threshold.
Proceedings of the 2002 IEEE Wireless Communications and Networking Conference Record, 2002
Proceedings of the 2002 IEEE Wireless Communications and Networking Conference Record, 2002
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002
Adaptively Increasing Performance and Scalability of Automatically Parallelized Programs.
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002
Proceedings of the International Symposium on Parallel Architectures, 2002
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002
2001
IEEE Trans. Computers, 2001
Proceedings of the 2001 International Conference on Image Processing, 2001
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001
2000
A watermarking sequence using parities of error control coding for image authentication and correction.
IEEE Trans. Consumer Electron., 2000
Iterative equalization-detection algorithm using trellis-based equalizer and RSC code for high density optical recording systems.
IEEE Trans. Consumer Electron., 2000
Fuzzy Sets Syst., 2000
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000
1999
Proceedings of the 1999 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP'99), 1999
1998
Int. J. Parallel Program., 1998
Proceedings of the 1998 IEEE International Conference on Communications, 1998
1997
Concurrent Static Single Assignment Form and Constant Propagation for Explicitly Parallel Programs.
Proceedings of the Languages and Compilers for Parallel Computing, 1997
1996
Proceedings of the 1996 International Conference on Parallel Processing Workshop, 1996
1995
Proceedings of the TAPSOFT'95: Theory and Practice of Software Development, 1995