Chanyang Park

According to our database, Chanyang Park authored at least 5 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

First Demonstration of Threshold Voltage Modeling in Multi-Hole V-NAND Flash Architecture with Noncircular Channel Hole Profiles.

Chanyang Park, Min-Kyu Jeong, Taein Lee, Sejun Park, Jung Hoon Lee, Yujin Lee, Seungwan Hong, Sunghoi Hur

Proceedings of the IEEE International Memory Workshop, 2025

2024

Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications.

Hyunseo You, Kihoon Nam, Jehyun An, Chanyang Park, Donghyun Kim, Seonhaeng Lee, Namhyun Lee, Rock-Hyun Baek

IEEE Access, 2024

2023

Modeling of 3D NAND Characteristics for Cross-Temperature by Using Graph Neural Network and Its Application.

Kyeongrae Cho, Jeong-Sik Lee, Chanyang Park, Hyeok Yun, Hyundong Jang, Seungjoon Eom, Min Sang Park, Hyun-Chul Choi, Rock-Hyun Baek

Adv. Intell. Syst., December, 2023

Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning.

Kihoon Nam, Chanyang Park, Hyeok Yun, Jun-Sik Yoon, Hyundong Jang, Kyeongrae Cho, Min Sang Park, Hyun-Chul Choi, Rock-Hyun Baek

IEEE Access, 2023

2022

Extraction of Device Structural Parameters Through DC/AC Performance Using an MLP Neural Network Algorithm.

Hyundong Jang, Hyeok Yun, Chanyang Park, Kyeongrae Cho, Kihoon Nam, Jun-Sik Yoon, Hyun-Chul Choi, Rock-Hyun Baek

IEEE Access, 2022