Rock-Hyun Baek
Orcid: 0000-0002-6175-8101Affiliations:
- Pohang University of Science and Technology, South Korea
According to our database1,
Rock-Hyun Baek
authored at least 22 papers
between 2018 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications.
IEEE Access, 2024
Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning.
IEEE Access, 2024
2023
Modeling of 3D NAND Characteristics for Cross-Temperature by Using Graph Neural Network and Its Application.
Adv. Intell. Syst., December, 2023
Accurate Prediction and Reliable Parameter Optimization of Neural Network for Semiconductor Process Monitoring and Technology Development.
Adv. Intell. Syst., September, 2023
Curing Process on Passivation Layer for Backside-Illuminated CMOS Image Sensor Application.
IEEE Access, 2023
Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning.
IEEE Access, 2023
Front-side and Back-side Power Delivery Network Guidelines for 2nm node High Perf Computing and Mobile SoC applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Sensors, 2022
Sensors, 2022
DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors.
IEEE Access, 2022
Extraction of Device Structural Parameters Through DC/AC Performance Using an MLP Neural Network Algorithm.
IEEE Access, 2022
2021
Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning.
IEEE Access, 2021
Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes.
IEEE Access, 2021
Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs.
IEEE Access, 2021
2020
A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications.
IEEE Access, 2020
Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications.
IEEE Access, 2020
Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application.
IEEE Access, 2020
IEEE Access, 2020
2019
Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node.
IEEE Access, 2019
Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node.
IEEE Access, 2019
Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain.
IEEE Access, 2019
2018
Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects.
Proceedings of the International SoC Design Conference, 2018