Chao-Chang Chiu
According to our database1,
Chao-Chang Chiu
authored at least 14 papers
between 2011 and 2018.
Collaborative distances:
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Bibliography
2018
94% power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
High Accuracy Knee Voltage Detection for Primary-Side Control in Flyback Battery Charger.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction.
IEEE Trans. Ind. Electron., 2016
2015
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
Self-Calibrated Knee Voltage Detector With 99.65% High Accuracy for AC Charger System in 0.5 µm 500 V UHV Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A compact power management for next generation intensive care unit with 91% conversion efficiency.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014
2013
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings.
IEEE J. Solid State Circuits, 2013
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement.
IEEE J. Solid State Circuits, 2013
Authentic mode-toggled detector with fast transient response under wide load range buck-boost converter.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System.
IEEE J. Solid State Circuits, 2012
A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance.
Proceedings of the Symposium on VLSI Circuits, 2012
A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
On-the-fly dynamic voltage scaling (DVS) in 65nm energy-efficient power management with frequency-based control (FBC) for SoC system.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011