Chao-Cheng Lee
According to our database1,
Chao-Cheng Lee
authored at least 42 papers
between 2005 and 2016.
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Bibliography
2016
12.7 A 96%-efficiency and 0.5%-current-cross-regulation single-inductor multiple floating-output LED driver with 24b color resolution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A Low-THD Class-D Audio Amplifier With Dual-Level Dual-Phase Carrier Pulsewidth Modulation.
IEEE Trans. Ind. Electron., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 0.003 mm<sup>2</sup> 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.
IEEE J. Solid State Circuits, 2015
Single-Inductor Quad-Output Switching Converter With Priority-Scheduled Program for Fast Transient Response and Unlimited Load Range in 40 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015
12.6 90% Peak efficiency single-inductor-multiple-output DC-DC buck converter with output independent gate drive control.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Implantable biomedical device supplying by a 28nm CMOS self-calibration DC-DC buck converter with 97% output voltage accuracy.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
99% High accuracy knee voltage detection for primary-side control in flyback converter.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Self-adjustable feed-forward control and auto-tracking off-time control techniques for 95% accuracy and 95% efficiency AC-DC non-isolated LED driver.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs.
Proceedings of the ESSCIRC Conference 2015, 2015
Suppressing output overshoot voltage technique with 47.1mW/μs power-recycling rate and 93% peak efficiency DC-DC converter for multi-core processors.
Proceedings of the ESSCIRC Conference 2015, 2015
Pseudo AC current synthesizer and DC offset-corrected technique in constant-on-time control buck converter for werable electronics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
99.4% peak audio signal recovery rate and ultra-low 0.32dB matching error with 10Hz high resolution filter fitting wearable aided speech compensation system.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
200nA low quiescent current deep-standby mode in 28nm DC-DC buck converter for active implantable medical devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
A direct AC-DC and DC-DC cross-source energy harvesting circuit with analog iterating-based MPPT technique with 72.5% conversion efficiency and 94.6% tracking efficiency.
Proceedings of the Symposium on VLSI Circuits, 2014
±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systems.
Proceedings of the Symposium on VLSI Circuits, 2014
A dual-level dual-phase pulse-width modulation class-D amplifier with 0.001% THD, 112 dB SNR.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A low THD clock-free Class-D audio amplifier with an increased damping resistor and cross offset cancellation technique.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A pseudo fixed switching frequency 2kHz/A in optimum on-time control buck converter with predicting correction technique for EMI solution.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology.
Proceedings of the ESSCIRC 2014, 2014
Anti-ESL/ESR variation robust constant-on-time control for DC-DC buck converter in 28nm CMOS technology.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
CCM/GM relative skip energy control in single-inductor multiple-output DC-DC converter for wearable device power solution.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
A 2.5W tablet speaker delivering 3.2W pseudo high power by psychoacoustic model based adaptive power management system.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings.
IEEE J. Solid State Circuits, 2013
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement.
IEEE J. Solid State Circuits, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System.
IEEE J. Solid State Circuits, 2012
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter.
IEEE J. Solid State Circuits, 2012
A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance.
Proceedings of the Symposium on VLSI Circuits, 2012
Inductorless and electrolytic capacitorless pseudo-sine current controller in LED lighting system with 1.1W/2.2W power reduction.
Proceedings of the 38th European Solid-State Circuit conference, 2012
A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2010
A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer.
IEEE J. Solid State Circuits, 2010
2008
A 2.4-GHz +25dBm P-1dB linear power amplifier with dynamic bias control in a 65-nm CMOS process.
Proceedings of the ESSCIRC 2008, 2008
2007
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005