Chen-Chih Huang

According to our database1, Chen-Chih Huang authored at least 23 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
99.4% peak audio signal recovery rate and ultra-low 0.32dB matching error with 10Hz high resolution filter fitting wearable aided speech compensation system.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A direct AC-DC and DC-DC cross-source energy harvesting circuit with analog iterating-based MPPT technique with 72.5% conversion efficiency and 94.6% tracking efficiency.
Proceedings of the Symposium on VLSI Circuits, 2014

±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systems.
Proceedings of the Symposium on VLSI Circuits, 2014

A dual-level dual-phase pulse-width modulation class-D amplifier with 0.001% THD, 112 dB SNR.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A low THD clock-free Class-D audio amplifier with an increased damping resistor and cross offset cancellation technique.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A pseudo fixed switching frequency 2kHz/A in optimum on-time control buck converter with predicting correction technique for EMI solution.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology.
Proceedings of the ESSCIRC 2014, 2014

A 2.5W tablet speaker delivering 3.2W pseudo high power by psychoacoustic model based adaptive power management system.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings.
IEEE J. Solid State Circuits, 2013

A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement.
IEEE J. Solid State Circuits, 2013

2012
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System.
IEEE J. Solid State Circuits, 2012

A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With ά-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control.
IEEE J. Solid State Circuits, 2012

An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter.
IEEE J. Solid State Circuits, 2012

A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance.
Proceedings of the Symposium on VLSI Circuits, 2012

Inductorless and electrolytic capacitorless pseudo-sine current controller in LED lighting system with 1.1W/2.2W power reduction.
Proceedings of the 38th European Solid-State Circuit conference, 2012

A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency.
IEEE J. Solid State Circuits, 2011

Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter.
IEEE J. Solid State Circuits, 2011

On-the-fly dynamic voltage scaling (DVS) in 65nm energy-efficient power management with frequency-based control (FBC) for SoC system.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System.
IEEE J. Solid State Circuits, 2010

2009
A high efficiency and compact size 65nm power management module with 1.2v low-voltage PWM controller for UWB system application.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2007
An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 10b 200MS/s pipelined folding ADC with offset calibration.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007


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