Cheena Singhal

According to our database, Cheena Singhal authored at least 4 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 252.8-GOPS and 10.1-TOPS/W Split DP-8T SRAM-Based Analog CIM Macro for 9-bit Signed MAC Operations With High Signal Margin.

Abhishek Goel, Cheena Singhal, Sparsh Mittal, Sudeb Dasgupta

IEEE Trans. Very Large Scale Integr. Syst., May, 2026

A 146 GOPS and 7.2 TOPS/W 6T SRAM-Based Analog CIM Macro Using Bit-Splitting for 8-Bit MAC Operations.

Cheena Singhal, Abhishek Goel, Sparsh Mittal, Sudeb Dasgupta

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2025

A 6T SRAM based reconfigurable in-memory XOR/XNOR and accumulation architecture.

Cheena Singhal, Sparsh Mittal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

A 6T SRAM Analog CIM Macro for 8-Bit MAC with Input/Weight Partitioning for High Signal Margin and Throughput.

Abhishek Goel, Cheena Singhal, Dinesh Kushwaha, Sparsh Mittal, Sudeb Dasgupta

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025