Chen-An Chen

According to our database, Chen-An Chen authored at least 4 papers between 2013 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 1.1 V-Programmable Metal-Fuse Technology With Current-Mode Programming and Program-Guarantee Technique in 28 nm CMOS Technology.

Philex Ming-Yan Fan, Chen-An Chen, Chih-Hao Wang, Hsiang-Yu Ko

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2025

2016

Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM.

Kun-Lun Luo, Ming-Hsueh Wu, Chun-Lung Hsu, Chen-An Chen

J. Electron. Test., 2016

2013

Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.

Chen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai, Liang-Chia Cheng

Proceedings of the 22nd Asian Test Symposium, 2013

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.

Bing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li

Proceedings of the 22nd Asian Test Symposium, 2013