Chun-Lung Hsu

According to our database¹, Chun-Lung Hsu authored at least 43 papers between 2003 and 2021.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2021

Fault-Aware Dependability Enhancement Techniques for Phase Change Memory.

[BibT_eX]

[DOI]

J. Electron. Test., 2021

Surface EMG vs. High-Density EMG: Tradeoff Between Performance and Usability for Head Orientation Prediction in VR Application.

[BibT_eX]

[DOI]

IEEE Access, 2021

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering.

[BibT_eX]

[DOI]

Katherine Shu-Min Li

Leon Li-Yang Chen

Ken Chau-Cheung Cheng

Proceedings of the 26th IEEE European Test Symposium, 2021

2020

Fault-Aware Dependability Enhancement Techniques for Flash Memories.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

ECC Caching Techniques for Protecting NAND Flash Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Head-Orientation-Prediction Based on Deep Learning on sEMG for Low-Latency Virtual Reality Application.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE International Conference on Robotic Computing, 2020

Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Testing of Configurable 8T SRAMs for In-Memory Computing.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

Testing of In-Memory-Computing 8T SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Testing stuck-open faults of priority address encoder in content addressable memories.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

Multiple-Wearable-Sensor-Based Gait Classification and Analysis in Patients with Neurological Disorders.

[BibT_eX]

[DOI]

Sensors, 2018

Diagnosis of Resistive Nonvolatile-8T SRAMs.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

2016

Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM.

[BibT_eX]

[DOI]

J. Electron. Test., 2016

2015

An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013

Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications.

[BibT_eX]

[DOI]

Chang-Hsin Cheng

Yu Liu

Chun-Lung Hsu

IEEE Trans. Very Large Scale Integr. Syst., 2012

Interlaced switch boxes placement for three-dimensional FPGA architecture design.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Yu-Sheng Huang

Fong-Chao Lee

Int. J. Circuit Theory Appl., 2012

2011

Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

High reliability built-in self-detection and self-correction design for DCT/IDCT application.

[BibT_eX]

[DOI]

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010

Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Chang-Hsin Cheng

Yu Liu

IEEE Trans. Very Large Scale Integr. Syst., 2010

Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip.

[BibT_eX]

[DOI]

Min-Ju Chan

Chun-Lung Hsu

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits.

[BibT_eX]

[DOI]

Hung-Yen Huang

Yu-Sheng Huang

Chun-Lung Hsu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

High-performance 3D-SRAM architecture design.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Ching-Fen Wu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Yi-Ting Lai

IEEE Trans. Instrum. Meas., 2009

Novel Built-In Current-Sensor-Based I<sub>DDQ</sub> Testing Scheme for CMOS Integrated Circuits.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Mean-Hom Ho

Chin-Feng Lin

IEEE Trans. Instrum. Meas., 2009

Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Ting-Hsuan Chen

IEEE Trans. Instrum. Meas., 2009

2008

A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Yu-Sheng Huang

J. Signal Process. Syst., 2008

Efficient built-in self-test for video coding cores: A case study on motion estimation computing array.

[BibT_eX]

[DOI]

Yu-Sheng Huang

Chen-Kai Chen

Chun-Lung Hsu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Mean-Hom Ho

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Mean-Hom Ho

Chin-Feng Lin

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Design of current-mode resonator for wireless applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design of Low-Frequency Low-Pass Filters for Biomedical Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Adaptive Low-Power Control Scheme for On-Chip Network Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Built-in self-test for phase-locked loops.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Yi-Ting Lai

Shu-Wei Wang

IEEE Trans. Instrum. Meas., 2005

Frequency-Scaling Approach for Managing Power Consumption in NOCs.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Wen-Tso Wang

Ying-Fu Hong

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004

Control and Observation Structure for Analog Circuits with Current Test Data.

[BibT_eX]

[DOI]

Chun-Lung Hsu

J. Electron. Test., 2004

2003

Design of High-Performance Charge-Pump Circuit for PLL Applications.

[BibT_eX]

[DOI]

Chun-Lung Hsu

Wu-Hung Lu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Chun-Lung Hsu

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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