Chun-Lung Hsu

According to our database1, Chun-Lung Hsu authored at least 35 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Fault-Aware Dependability Enhancement Techniques for Flash Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

ECC Caching Techniques for Protecting NAND Flash Memories.
Proceedings of the IEEE International Test Conference in Asia, 2020

2019
Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM.
J. Electron. Test., 2019

Testing of In-Memory-Computing 8T SRAMs.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Testing stuck-open faults of priority address encoder in content addressable memories.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018
Multiple-Wearable-Sensor-Based Gait Classification and Analysis in Patients with Neurological Disorders.
Sensors, 2018

Diagnosis of Resistive Nonvolatile-8T SRAMs.
Proceedings of the International SoC Design Conference, 2018

2016
Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM.
J. Electron. Test., 2016

2015
An efficient 3D-IC on-chip test framework to embed TSV testing in memory BIST.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.
Proceedings of the 22nd Asian Test Symposium, 2013

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Interlaced switch boxes placement for three-dimensional FPGA architecture design.
Int. J. Circuit Theory Appl., 2012

2011
Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder.
IEEE Trans. Computers, 2011

High reliability built-in self-detection and self-correction design for DCT/IDCT application.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010
Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

High-performance 3D-SRAM architecture design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application.
IEEE Trans. Instrum. Meas., 2009

Novel Built-In Current-Sensor-Based I<sub>DDQ</sub> Testing Scheme for CMOS Integrated Circuits.
IEEE Trans. Instrum. Meas., 2009

Built-in Self-Test Design for Fault Detection and Fault Diagnosis in SRAM-Based FPGA.
IEEE Trans. Instrum. Meas., 2009

2008
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications.
J. Signal Process. Syst., 2008

Efficient built-in self-test for video coding cores: A case study on motion estimation computing array.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006
New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Design of current-mode resonator for wireless applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design of Low-Frequency Low-Pass Filters for Biomedical Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Adaptive Low-Power Control Scheme for On-Chip Network Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Built-in self-test for phase-locked loops.
IEEE Trans. Instrum. Meas., 2005

Frequency-Scaling Approach for Managing Power Consumption in NOCs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004
Control and Observation Structure for Analog Circuits with Current Test Data.
J. Electron. Test., 2004


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