Bing-Chuan Bai

Orcid: 0000-0001-6961-2898

According to our database1, Bing-Chuan Bai authored at least 6 papers between 2007 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.
Proceedings of the 22nd Asian Test Symposium, 2013

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.
Proceedings of the 22nd Asian Test Symposium, 2013

2009
Power scan: DFT for power switches in VLSI designs.
Proceedings of the 2009 IEEE International Test Conference, 2009

Fault modeling and testing of retention flip-flops in low power designs.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A Two-level Simultaneous Test Data and Time Reduction Technique for SOC.
J. Inf. Sci. Eng., 2008

2007
Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique.
Proceedings of the 16th Asian Test Symposium, 2007


  Loading...