Kun-Lun Luo

According to our database, Kun-Lun Luo authored at least 7 papers between 2004 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2016

Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM.

Kun-Lun Luo, Ming-Hsueh Wu, Chun-Lung Hsu, Chen-An Chen

J. Electron. Test., 2016

2013

Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.

Chen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai, Liang-Chia Cheng

Proceedings of the 22nd Asian Test Symposium, 2013

Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM.

Bing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li

Proceedings of the 22nd Asian Test Symposium, 2013

2011

A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories.

Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu

IEEE Trans. Very Large Scale Integr. Syst., 2011

2007

A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.

Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu

IEEE Trans. Very Large Scale Integr. Syst., 2007

2006

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu

Proceedings of the 2006 IEEE International Test Conference, 2006

2004

Fail Pattern Identification for Memory Built-In Self-Repair.

Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004