Chen Dong

  • University of Illinois, Urbana-Champaign, Department of Electrical and Computer Engineering, IL, USA
  • Purdue University at Indianapolis, Department of Electrical and Computer Engineering, IN, USA

According to our database1, Chen Dong authored at least 15 papers between 2006 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance.
Int. J. Reconfigurable Comput., 2012

Architecture and performance evaluation of 3D CMOS-NEM FPGA.
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011

SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Architecture and CAD for Nanoscale and Three-Dimensional FPGA
PhD thesis, 2010

Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Clock tree synthesis under aggressive buffer insertion.
Proceedings of the 47th Design Automation Conference, 2010

Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture.
Int. J. Parallel Program., 2009

Variation Aware Routing for Three-Dimensional FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

FPCNA: a field programmable carbon nanotube array.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Reconfigurable circuit design with nanomaterials.
Proceedings of the Design, Automation and Test in Europe, 2009

3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Exploring carbon nanotubes and NiSi nanowires as on-chip interconnections.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006