Lei He

Orcid: 0000-0002-5266-3805

Affiliations:
  • University of California, Los Angeles, Department of Electrical Engineering, CA, USA
  • University of Wisconsin, Madison, WI, USA (1999 - 2002)


According to our database1, Lei He authored at least 269 papers between 1996 and 2023.

Collaborative distances:

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Bibliography

2023
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator.
ACM Trans. Reconfigurable Technol. Syst., March, 2023

Progressive Energy-Based Cooperative Learning for Multi-Domain Image-to-Image Translation.
CoRR, 2023

Oral-NeXF: 3D Oral Reconstruction with Neural X-ray Field from Panoramic Imaging.
CoRR, 2023

MDT-Net: Multi-Domain Transfer by Perceptual Supervision for Unpaired Images in OCT Scan.
Proceedings of the 20th IEEE International Symposium on Biomedical Imaging, 2023

Token Packing for Transformers with Variable-Length Inputs.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

2022
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration.
ACM Trans. Reconfigurable Technol. Syst., 2022

A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation.
ACM Trans. Design Autom. Electr. Syst., 2022

Effective Scaling of Blockchain Beyond Consensus Innovations and Moore's Law: Challenges and Opportunities.
IEEE Syst. J., 2022

An IoT-based intelligent irrigation system with data fusion and a self-powered wide-area network.
J. Ind. Inf. Integr., 2022

BCmaster: A Compatible Framework for Comprehensively Analyzing and Monitoring Blockchain Systems in IoT.
IEEE Internet Things J., 2022

TreeMoCo: Contrastive Neuron Morphology Representation Learning.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

ReMix: A General and Efficient Framework for Multiple Instance Learning Based Whole Slide Image Classification.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2022, 2022

SkeletonGCN: A Simple Yet Effective Accelerator For GCN Training.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

ConCL: Concept Contrastive Learning for Dense Prediction Pre-training in Pathology Images.
Proceedings of the Computer Vision - ECCV 2022, 2022

2021
Channel-Correlation-Enabled Transmission Optimization for MISO Wiretap Channels.
IEEE Trans. Wirel. Commun., 2021

Editorial for FGCS special issue: Computation Intelligence for Energy Internet.
Future Gener. Comput. Syst., 2021

LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator.
CoRR, 2021

Atlas-aware ConvNetfor Accurate yet Robust Anatomical Segmentation.
CoRR, 2021

OralViewer: 3D Demonstration of Dental Surgeries for Patient Education with Oral Cavity Reconstruction from a 2D Panoramic X-ray.
CoRR, 2021

Exploring Forensic Dental Identification with Deep Learning.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

TumorCP: A Simple but Effective Object-Level Data Augmentation for Tumor Segmentation.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2021 - 24th International Conference, Strasbourg, France, September 27, 2021

OralViewer: 3D Demonstration of Dental Surgeries for Patient Education with Oral Cavity Reconstruction from a 2D Panoramic X-ray.
Proceedings of the IUI '21: 26th International Conference on Intelligent User Interfaces, 2021

Exploring Instance-Level Uncertainty for Medical Detection.
Proceedings of the 18th IEEE International Symposium on Biomedical Imaging, 2021

T-Net: Learning Feature Representation With Task-Specific Supervision For Biomedical Image Analysis.
Proceedings of the 18th IEEE International Symposium on Biomedical Imaging, 2021

MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

NPE: An FPGA-based Overlay Processor for Natural Language Processing.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Heterogeneous Dual-Core Overlay Processor for Light-Weight CNNs.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Oral-3D: Reconstructing the 3D Structure of Oral Cavity from Panoramic X-ray.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020
Robust Beamforming Design for Correlated MISO Wiretap Channels Under Channel Uncertainty.
IEEE Wirel. Commun. Lett., 2020

Correlation-Based Secure Transmission for Correlated MISO Wiretap Channels.
IEEE Wirel. Commun. Lett., 2020

Correlation-Based Cooperative Jamming to Enhance Secrecy With Receiver-Side Correlation.
IEEE Trans. Veh. Technol., 2020

Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

QoS-Based Robust Cooperative-Jamming-Aided Beamforming for Correlated Wiretap Channels.
IEEE Signal Process. Lett., 2020

Accurate Anchor Free Tracking.
CoRR, 2020

Oral-3D: Reconstructing the 3D Bone Structure of Oral Cavity from 2D Panoramic X-ray.
CoRR, 2020

T-Net: A Template-Supervised Network for Task-specific Feature Extraction in Biomedical Image Analysis.
CoRR, 2020

Effective scaling of blockchain beyond consensus innovations and Moore's law.
CoRR, 2020

X2Teeth: 3D Teeth Reconstruction from a Single Panoramic Radiograph.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2020, 2020

A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural Networks.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

OralCam: Enabling Self-Examination and Awareness of Oral Health Using a Smartphone Camera.
Proceedings of the CHI '20: CHI Conference on Human Factors in Computing Systems, 2020

Atlas-aware ConvNet for Accurate yet Robust Anatomical Segmentation.
Proceedings of The 12th Asian Conference on Machine Learning, 2020

2019
Multiple-Jammer-Aided Secure Transmission With Receiver-Side Correlation.
IEEE Trans. Wirel. Commun., 2019

AN-Aided Secure Beamforming Design for Correlated MISO Wiretap Channels.
IEEE Commun. Lett., 2019

Channel-Correlation-Enabled Transmit Optimization for MISO Wiretap Channels.
CoRR, 2019

CompareNet: Anatomical Segmentation Network with Deep Non-local Label Fusion.
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2019, 2019

Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis.
Proceedings of the 2019 International Symposium on Physical Design, 2019

Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method.
Proceedings of the International Conference on Computer-Aided Design, 2019

Timing-Aware Fill Insertions with Design-Rule and Density Constraints.
Proceedings of the International Conference on Computer-Aided Design, 2019

Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2019

Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Probabilistic Model Checking and Scheduling Implementation of an Energy Router System in Energy Internet for Green Cities.
IEEE Trans. Ind. Informatics, 2018

Recurrent Neural Networks with Pre-trained Language Model Embedding for Slot Filling Task.
CoRR, 2018

IEEE Access Special Section Editorial: The Internet of Energy: Architectures, Cyber Security, and Applications - Part II.
IEEE Access, 2018

IEEE Access Special Section Editorial: The Internet of Energy: Architectures, Cyber Security, and Applications.
IEEE Access, 2018

Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

A fast and robust failure analysis of memory circuits using adaptive importance sampling method.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Layout driven FPGA packing algorithm for performance optimization.
IEICE Electron. Express, 2017

Grain Price Forecasting Using a Hybrid Stochastic Method.
Asia Pac. J. Oper. Res., 2017

Modeling and Implementation of Electroactive Smart Air-Conditioning Vent Register for Personalized HVAC Systems.
IEEE Access, 2017

Probabilistic Model Checking for Green Energy Router System in Energy Internet.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Sampling and Reconstruction in Arbitrary Measurement and Approximation Spaces Associated With Linear Canonical Transform.
IEEE Trans. Signal Process., 2016

LLSPLAT: Improving Concolic Testing by Bounded Model Checking.
Proceedings of the 16th IEEE International Working Conference on Source Code Analysis and Manipulation, 2016

Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

FPGA Power Estimation Using Automatic Feature Selection (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

A quantum annealing approach for boolean satisfiability problem.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
A Game Theory-Based Energy Management System Using Price Elasticity for Smart Grids.
IEEE Trans. Ind. Informatics, 2015

An improved spray and wait algorithm based on RVNS in Delay Tolerant Mobile Sensor Networks.
Proceedings of the 2015 IEEE International Conference on Communications, 2015

A Social Awareness based Feedback Mechanism for delivery reliability in Delay Tolerant Networks.
Proceedings of the 2015 IEEE International Conference on Communications, 2015

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Statistical timing and power analysis of VLSI considering non-linear dependence.
Integr., 2014

Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges.
IEEE Des. Test, 2014

Accelerating the iterative linear solver for reservoir simulation on multicore architectures.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A fast and provably bounded failure analysis of memory circuits in high dimensions.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Modeling and Application of Multi-Port TSV Networks in 3-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty.
Integr., 2013

Fast Filter-Based Boolean Matchers.
IEEE Embed. Syst. Lett., 2013

Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms.
IEEE Des. Test, 2013

Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Inconspicuous Personal Computer Protection with Touch-Mouse.
Proceedings of the Human Aspects of Information Security, Privacy, and Trust, 2013

2012
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Statistical Timing and Power Optimization of Architecture and Device for FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2012

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.
ACM Trans. Design Autom. Electr. Syst., 2012

A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials.
ACM Trans. Design Autom. Electr. Syst., 2012

NeuroGlasses: A Neural Sensing Healthcare System for 3-D Vision Technology.
IEEE Trans. Inf. Technol. Biomed., 2012

Smart insole: a wearable system for gait analysis.
Proceedings of the 5th International Conference on PErvasive Technologies Related to Assistive Environments, 2012

A fast estimation of SRAM failure rate using probability collectives.
Proceedings of the International Symposium on Physical Design, 2012

Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator.
IEEE Trans. Very Large Scale Integr. Syst., 2011

In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

System-in-Package: Electrical and Layout Perspectives.
Found. Trends Electron. Des. Autom., 2011

Stochastic analog circuit behavior modeling by point estimation method.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Mitigating FPGA interconnect soft errors by in-place LUT inversion.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Acceleration of Multi-agent Simulation on FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Fault modeling and characteristics of SRAM-based FPGAs (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials.
Proceedings of the 48th Design Automation Conference, 2011

2010
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling.
IEEE Trans. Very Large Scale Integr. Syst., 2010

EMPIRE: An Efficient and Compact Multiple-Parameterized Model-Order Reduction Method for Physical Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Effective congestion reduction for IC package substrate routing.
ACM Trans. Design Autom. Electr. Syst., 2010

Optimality and Improvement of Dynamic Voltage Scaling Algorithms for Multimedia Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Accelerating Boolean Matching Using Bloom Filter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Engineering a scalable Boolean matching based on EDA SaaS 2.0.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Modeling and design for beyond-the-die power integrity.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

In-place decomposition for robustness in FPGA.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Building a faster boolean matcher using bloom filter.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications.
Proceedings of the Design, Automation and Test in Europe, 2010

A universal state-of-charge algorithm for batteries.
Proceedings of the 47th Design Automation Conference, 2010

Rewiring for robustness.
Proceedings of the 47th Design Automation Conference, 2010

QuickYield: an efficient global-search based parametric yield estimation with performance constraints.
Proceedings of the 47th Design Automation Conference, 2010

Fault-tolerant resynthesis with dual-output LUTs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

On confidence in characterization and application of variation models.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity.
ACM Trans. Design Autom. Electr. Syst., 2009

Substrate Topological Routing for High-Density Packages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Efficient Additive Statistical Leakage Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Robust On-Chip Signaling by Staggered and Twisted Bundle.
IEEE Des. Test Comput., 2009

Worst case timing jitter and amplitude noise in differential signaling.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Simultaneous test pattern compaction, ordering and X-filling for testing power reduction.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Diffusion-driven congestion reduction for substrate topological routing.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Joint design-time and post-silicon optimization for digitally tuned analog circuits.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

IPR: In-Place Reconfiguration for FPGA fault tolerance.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation.
Proceedings of the 46th Design Automation Conference, 2009

Incremental and on-demand random walk for iterative power distribution network analysis.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Accounting for non-linear dependence using function driven component analysis.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.
ACM Trans. Design Autom. Electr. Syst., 2008

Dual-V<sub>dd</sub> Buffer Insertion for Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fashion: A Fast and Accurate Solution to Global Routing Problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Robust FPGA resynthesis based on fault-tolerant Boolean matching.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Topological routing to maximize routability for package substrate.
Proceedings of the 45th Design Automation Conference, 2008

FPGA area reduction by multi-output function based sequential resynthesis.
Proceedings of the 45th Design Automation Conference, 2008

Scalable Symbolic Model Order Reduction.
Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008

2007
Microarchitecture Configurations and Floorplanning Co-Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Circuit-simulated obstacle-aware Steiner routing.
ACM Trans. Design Autom. Electr. Syst., 2007

Robust Extraction of Spatial Correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Field Programmability of Supply Voltages for FPGA Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L<sub>eff</sub> Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Device and Architecture Cooptimization for FPGA Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Full-chip multilevel routing for power and signal integrity.
Integr., 2007

Statistical placement for FPGAs considering.
IET Comput. Digit. Tech., 2007

Fast dual-vdd buffering based on interconnect prediction and sampling.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Minimal skew clock embedding considering time variant temperature gradient.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Empire: an efficient and compact multiple-parameterized model order reduction method.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Device and architecture concurrent optimization for FPGA transient soft error rate.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Temperature aware microprocessor floorplanning considering application dependent power load.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design.
Proceedings of the 44th Design Automation Conference, 2007

Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources.
Proceedings of the 44th Design Automation Conference, 2007

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Wideband passive multiport model order reduction and realization of RLCM circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Modeling and synthesis of multiport transmission line for multichannel communication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Fast buffer insertion considering process variations.
Proceedings of the 2006 International Symposium on Physical Design, 2006

SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Noise driven in-package decoupling capacitor optimization for power integrity.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Power-efficient pulse width modulation DC/DC converters with zero voltage switching control.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

A fast block structure preserving model order reduction for inverse inductance circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Simultaneous power and thermal integrity driven via stapling in 3D ICs.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Placement and Timing for FPGAs Considering Variations.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

FPGA Performance Optimization Via Chipwise Placement Considering Process Variations.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Fast analysis of structured power grid by triangularization based structure preserving model order reduction.
Proceedings of the 43rd Design Automation Conference, 2006

Circuit simulation based obstacle-aware Steiner routing.
Proceedings of the 43rd Design Automation Conference, 2006

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction.
Proceedings of the 43rd Design Automation Conference, 2006

Constraint driven I/O planning and placement for chip-package co-design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Extended global routing with RLC crosstalk constraints.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Circuits and architectures for field programmable gate array with configurable supply voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Microarchitecture-level leakage reduction with data retention.
IEEE Trans. Very Large Scale Integr. Syst., 2005

A provably passive and cost-efficient model for inductive interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Temperature and supply Voltage aware performance and power modeling at microarchitecture level.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Power modeling and characteristics of field programmable gate arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Worst case crosstalk noise for nonswitching victims in high-speed buses.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Piecewise linear model for transmission line with capacitive loading and ramp input.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Microarchitecture Level Interconnect Modeling Considering Layout Optimization.
J. Low Power Electron., 2005

Micro-architecture Performance Estimation by Formula.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Modeling and Design of Chip-Package Interface.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Challenges and opportunities for low power FPGAs in nanometer technologies.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Power-optimal repeater insertion considering Vdd and Vth as design freedoms.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A sparsified vector potential equivalent circuit model for massively coupled interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

FPGA device and architecture evaluation considering process variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Buffer Insertion Considering Process Variation.
Proceedings of the 2005 Design, 2005

Scheduling of Soft Real-Time Systems for Context-Aware Applications.
Proceedings of the 2005 Design, 2005

Power optimal dual-Vdd buffered tree considering buffer stations and blockages.
Proceedings of the 42nd Design Automation Conference, 2005

Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction.
Proceedings of the 42nd Design Automation Conference, 2005

Device and architecture co-optimization for FPGA power reduction.
Proceedings of the 42nd Design Automation Conference, 2005

A wideband hierarchical circuit reduction for massively coupled interconnects.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Probabilistic congestion model considering shielding for crosstalk reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Distributed sleep transistor network for power reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.
ACM Trans. Design Autom. Electr. Syst., 2004

Full-chip routing optimization with RLC crosstalk budgeting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

On optimal physical synthesis of sleep transistors.
Proceedings of the 2004 International Symposium on Physical Design, 2004

Shielding area optimization under the solution of interconnect crosstalk.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Performance and RLC crosstalk driven global routing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Vdd programmability to reduce FPGA interconnect power.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Low-power technology mapping for FPGA architectures with dual supply voltages.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects.
Proceedings of the 41th Design Automation Conference, 2004

FPGA power reduction using configurable dual-Vdd.
Proceedings of the 41th Design Automation Conference, 2004

System level leakage reduction considering the interdependence of temperature and leakage.
Proceedings of the 41th Design Automation Conference, 2004

High-level area and power-up current estimation considering rich cell library.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Modeling of coplanar waveguide for buffered clock tree.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
High Level Area and Current Estimation.
Proceedings of the Integrated Circuit and System Design, 2003

Coupled Power and Thermal Simulation with Active Cooling.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Microarchitecture level power and thermal simulation considering temperature dependent leakage model.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Architecture evaluation for power-efficient FPGAs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Vector potential equivalent circuit based on PEEC inversion.
Proceedings of the 40th Design Automation Conference, 2003

Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Estimation of Maximum Power-Up Current.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Post global routing RLC crosstalk budgeting.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Leakage power modeling and reduction with data retention.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A decoupling method for analysis of coupled RLC interconnects.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Towards global routing with RLC crosstalk constraints.
Proceedings of the 39th Design Automation Conference, 2002

2001
Interconnect sizing and spacing with consideration of couplingcapacitance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Simultaneous signal and power routing under K model.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Instruction Prediction for Step Power Reduction.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Maximum current estimation considering power gating.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Pre-routing Estimation of Shielding for RLC Signal Integrity.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

An efficient model for frequency-dependent on-chip inductance.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint.
Proceedings of the 38th Design Automation Conference, 2001

An efficient analytical model of coupled on-chip RLC interconnects.
Proceedings of ASP-DAC 2001, 2001

2000
Ramp Up/Down Functional Unit to Reduce Step Power.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.
Proceedings of the 2000 International Symposium on Physical Design, 2000

Clocktree RLC Extraction with Efficient Inductance Modeling.
Proceedings of the 2000 Design, 2000

1999
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An efficient inductance modeling for on-chip interconnects.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
An efficient technique for device and interconnect optimization in deep submicron designs.
Proceedings of the 1998 International Symposium on Physical Design, 1998

1997
Interconnect design for deep submicron ICs.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Global interconnect sizing and spacing with consideration of coupling capacitance.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Optimal wiresizing for interconnects with multiple sources.
ACM Trans. Design Autom. Electr. Syst., 1996

Performance optimization of VLSI interconnect layout.
Integr., 1996

An efficient approach to simultaneous transistor and interconnect sizing.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996


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