Cheng-Chi Wong

According to our database, Cheng-Chi Wong authored at least 7 papers between 2007 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder.

Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang

IEEE Trans. Circuits Syst. II Express Briefs, 2015

2013

A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis.

Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang

IEEE J. Solid State Circuits, 2013

2011

High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver.

Cheng-Chi Wong, Hsie-Chia Chang

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

2010

Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System.

Cheng-Chi Wong, Hsie-Chia Chang

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.

Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee

IEEE J. Solid State Circuits, 2010

A multiple code-rate turbo decoder based on reciprocal dual trellis architecture.

Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2007

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver.

Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007