Chen-Yi Lee

According to our database1, Chen-Yi Lee authored at least 210 papers between 1990 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Few-Shot and Continual Learning with Attentive Independent Mechanisms.
CoRR, 2021

2020
FADE: Feature Aggregation for Depth Estimation With Multi-View Stereo.
IEEE Trans. Image Process., 2020

Feature Consistency Training With JPEG Compressed Images.
IEEE Trans. Circuits Syst. Video Technol., 2020

Multitarget Sample Preparation Using MEDA Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Real-Time Wearable Assist System for Upper Extremity Throwing Action Based on Accelerometers.
Sensors, 2020

Convolutional neural networks for classification of music-listening EEG: comparing 1D convolutional kernels with 2D kernels and cerebral laterality of musical influence.
Neural Comput. Appl., 2020

An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Cross-Domain Adaptation for Biometric Identification Using Photoplethysmogram.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

Meta-rPPG: Remote Heart Rate Estimation Using a Transductive Meta-learner.
Proceedings of the Computer Vision - ECCV 2020, 2020

NeuralScale: Efficient Scaling of Neurons for Resource-Constrained Deep Neural Networks.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

2019
QuatNet: Quaternion-Based Head Pose Estimation With Multiregression Loss.
IEEE Trans. Multim., 2019

Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques.
IEEE Trans. Biomed. Circuits Syst., 2019

A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Centralized State Sensing using Sensor Array on Wearable Device.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Joint Capacitive Sensing and Frequency Selection for Fast Medical Tests.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Short-time-span EEG-based personalized emotion recognition with deep convolutional neural network.
Proceedings of the 2019 IEEE International Conference on Signal and Image Processing Applications, 2019

Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control.
IEEE J. Solid State Circuits, 2018

A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Confnet: Predict with Confidence.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Correlation-Based Face Detection for Recognizing Faces in Videos.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Diabetic Retinopathy Detection Based on Deep Convolutional Neural Networks.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

2017
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits Syst., 2017

Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits Syst., 2017

A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications.
IEEE J. Solid State Circuits, 2017

Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Design considerations and clinical applications of closed-loop neural disorder control SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A Variation-Tolerant Subthreshold to Superthreshold Level Shifter for Heterogeneous Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Built-in self-test for micro-electrode-dot-array digital microfluidic biochips.
Proceedings of the 2016 IEEE International Test Conference, 2016

Design of a micro-electrode cell for programmable lab-on-CMOS platform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Error recovery in a micro-electrode-dot-array digital microfluidic biochip?
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

High-level synthesis for micro-electrode-dot-array digital microfluidic biochips.
Proceedings of the 53rd Annual Design Automation Conference, 2016

A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
An Intelligent Digital Microfluidic Processor for Biomedical Detection.
J. Signal Process. Syst., 2015

An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Efficient Hardware Architecture of η<sub>T</sub> Pairing Accelerator Over Characteristic Three.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Hardware-Efficient Sigmoid Function With Adjustable Precision for a Neural Network System.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver.
Proceedings of the VLSI Design, Automation and Test, 2015

A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications.
Proceedings of the ESSCIRC Conference 2015, 2015

A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications.
IEEE J. Solid State Circuits, 2014

A 7.11mJ/Gb/query data-driven machine learning processor (D<sup>2</sup>MLP) for big data analysis and applications.
Proceedings of the Symposium on VLSI Circuits, 2014

Event-driven read-out circuits for energy-efficient sensor-SoC's.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 2 GOPS quad-mean shift processor with early termination for machine learning applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

What is a good way to expand a silicon value to a solution value?
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan.
IEEE Access, 2013

A digital microfluidic processor for biomedical applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Processor with side-channel attack resistance.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Low-Power DCO Using Interlaced Hysteresis Delay Cells.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits, 2012

A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder.
IEEE J. Solid State Circuits, 2012

A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications.
Proceedings of the Symposium on VLSI Circuits, 2012

A low cost DPA-resistant 8-bit AES core based on ring oscillators.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Spatial Isolation on Realtime Hypervisor using Core-local Memory.
Proceedings of the PECCS 2012, 2012

Extrinsic data compression method for double-binary turbo codes.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Stochastic decoding for LDPC convolutional codes.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

A 4.88µW ECG delineator using wavelet transform for mobile healthcare application.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

A memory-efficient architecture for intra predictor and de-blocking filter in video coding system.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications.
J. Signal Process. Syst., 2011

A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Predefined Bit-Plane Comparison Coding for Mobile Video Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters.
IEEE J. Solid State Circuits, 2011

A low-power all-digital phase modulator pair for LINC transmitters.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applications.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2011

An area-efficient high-accuracy prediction-based CABAC decoder architecture for H.264/AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A low power all-digital signal component separator for uneven multi-level LINC systems.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A micropower biomedical signal processor for mobile healthcare applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 0.67mW 14.55Mbps OFDM-based sensor node transmitter for body channel communications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Sub-10-muhboxW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.
IEEE J. Solid State Circuits, 2010

A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System.
IEEE J. Solid State Circuits, 2010

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder.
J. Low Power Electron., 2010

Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications.
IEICE Electron. Express, 2010

Tunable magnetic alginate microspheres by using a microfluidic device.
Proceedings of the 5th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2010

An improved soft BCH decoder with one extra error compensation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications.
IEEE J. Solid State Circuits, 2009

An eCrystal Oscillator with Self-calibration Capability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Design of an Intra Predictor with Data Reuse for High-profile H.264 Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

A 11.5-Gbps LDPC decoder based on CP-PEG code construction.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

A 0.92mm<sup>2</sup> 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead.
J. Signal Process. Syst., 2008

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications.
IEEE J. Solid State Circuits, 2008

A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems.
IEEE J. Solid State Circuits, 2008

Multi-mode message passing switch networks applied for QC-LDPC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An all digital spread spectrum clock generator with programmable spread ratio for SoC applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Design of a memory-based VLC decoder for portable video applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A New Soft Variable Length Decoder for Wireless Video Transmission.
IEEE Trans. Circuits Syst. Video Technol., 2007

An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule.
IEEE Trans. Circuits Syst. Video Technol., 2007

An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Design of an FFT/IFFT Processor for MIMO OFDM Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A 125 µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications.
IEEE J. Solid State Circuits, 2007

MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Design of a DVB-T/H COFDM Receiver for Portable Video Applications [Topics in Circuits for Communications].
IEEE Commun. Mag., 2007

An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems.
Proceedings of the 2007 IEEE International SOC Conference, 2007

A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A low power turbo/Viterbi decoder for 3GPP2 applications.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A Context Adaptive Bit-Plane Coder With Maximum-Likelihood-Based Stochastic Bit-Reshuffling Technique for Scalable Video Coding.
IEEE Trans. Multim., 2006

A Low-Complexity Synchronizer for OFDM-Based UWB System.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications.
IEEE J. Solid State Circuits, 2006

A low-power dual-mode video decoder for mobile applications.
IEEE Commun. Mag., 2006

A 125µw, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications.
Proceedings of the 43rd Design Automation Conference, 2006

A Self-Grouping and Table-Merging Algorithm for VLC-Based Video Decoding System.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Guest Editorial: System-on-a-Chip for Multimedia Systems.
J. VLSI Signal Process., 2005

Design of a power-reduction Viterbi decoder for WLAN applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A portable digitally controlled oscillator using novel varactors.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A novel technique for I/Q imbalance and CFO compensation in OFDM systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A new motion compensation design for H.264/AVC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A memory-efficient deblocking filter for H.264/AVC video coding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An H.264/AVC decoder with 4×4-block level pipeline.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Predictive equalizer design for DVB-T system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An area-efficient and high-throughput de-blocking filter for multi-standard video applications.
Proceedings of the 2005 International Conference on Image Processing, 2005

2004
Enhanced Stochastic Bit Reshuffling for Fine Granular Scalable Video Coding.
Proceedings of the Advances in Multimedia Information Processing - PCM 2004, 5th Pacific Rim Conference on Multimedia, Tokyo, Japan, November 30, 2004

A power and area efficient multi-mode FEC processor.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A low-power group-based VLD design.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A low-complexity soft vlc decoder using performance modeling.
Proceedings of the 2004 International Conference on Image Processing, 2004

2003
Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware.
Vis. Comput., 2003

Error-resilient image coding (ERIC) with smart-IDCT error concealment technique for wireless multimedia transmission.
IEEE Trans. Circuits Syst. Video Technol., 2003

A Low-Power Design for Reed-Solomon Decoders.
J. Circuits Syst. Comput., 2003

Infrastructure for Education and Research of SOC/IP in Taiwan.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

A Design of CMOS Broadband Amplifier With High-Q Active Inductor.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A JPEG-like texture compression with adaptive quantization for 3D graphics application.
Vis. Comput., 2002

Reduce the Memory Bandwidth of 3D Graphics Hardware with a Novel Rasterizer.
J. Circuits Syst. Comput., 2002

A high throughput context-based adaptive arithmetic codec for JPEG2000.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A novel fixed bit plane error resilient image coding for wireless multimedia transmission.
Proceedings of the 2002 International Conference on Image Processing, 2002

A high throughput low cost context-based adaptive arithmetic codec for multiple standards.
Proceedings of the 2002 International Conference on Image Processing, 2002

Error resilient image coding and smart post-processing error concealment for wireless image transmission.
Proceedings of the IEEE International Conference on Acoustics, 2002

A novel DCT-based bit plane error resilient entropy coding for wireless multimedia communication.
Proceedings of the IEEE International Conference on Acoustics, 2002

FPGA education and research activities in Taiwan.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2001
A new approach of group-based VLC codec system with full table programmability.
IEEE Trans. Circuits Syst. Video Technol., 2001

A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A wideband digital frequency synthesizer.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A novel structure for portable digitally controlled oscillator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A novel subcircuit extraction algorithm by recursive identification scheme.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A high-throughput memory-based VLC decoder with codeword boundary prediction.
IEEE Trans. Circuits Syst. Video Technol., 2000

A new approach of group-based VLC codec system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Construction of Error Resilient Synchronization Codeword for Variable-Length Code in Image Transmission.
Proceedings of the 2000 International Conference on Image Processing, 2000

HVLC: error correctable hybrid variable length code for image coding in wireless transmission.
Proceedings of the IEEE International Conference on Acoustics, 2000

FORTE-VLC: A forward tracing self-error correction variable length code for image coding in wireless application.
Proceedings of the 10th European Signal Processing Conference, 2000

1999
Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms.
IEEE Trans. Very Large Scale Integr. Syst., 1999

A New Anti-Aliasing Algorithm for Computer Graphics Images.
Proceedings of the 1999 International Conference on Image Processing, 1999

An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform.
Proceedings of the 1999 International Conference on Image Processing, 1999

A Cost-Effective Lighting Processor for 3D Graphics Application.
Proceedings of the 1999 International Conference on Image Processing, 1999

An efficient VLC decompression scheme for user-defined coding tables.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1998
Entropy-constrained gradient-match vector quantization for image coding.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

1997
An Efficient VLSI Architecture for Full-Search Block Matching Algorithms.
J. VLSI Signal Process., 1997

A multicasting solution for ATM video applications.
IEEE Trans. Circuits Syst. Video Technol., 1997

Buffer size optimization for full-search block matching algorithms.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Finite state vector quantization with multipath tree search strategy for image/video coding.
IEEE Trans. Circuits Syst. Video Technol., 1996

The outage probability in DS/CDMA for cellular mobile radio with imperfect power control.
Proceedings of the 7th IEEE International Symposium on Personal, 1996

Scalable VLSI architectures for full-search block matching algorithms.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

1995
A shift register architecture for high-speed data sorting.
J. VLSI Signal Process., 1995

An Efficient Memory Architecture for Motion Estimation Processor Design.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A New Multi-Path Tree-Search FSVQ Architecture for Image/Video Sequence Coding.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Semi-systolic array based motion estimation processor design.
Proceedings of the 1995 International Conference on Acoustics, 1995

1994
High-speed median filter designs using shiftable content-addressable memory.
IEEE Trans. Circuits Syst. Video Technol., 1994

High-Throughput Data Compressor Designs Using Content Addressable Memory.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Finite State Vector Quantization with Multi-Path Tree Search Strategy for Image/Video Coding.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
VLSI implementation of an M-array image filter based on shift register array.
Integr., 1993

An area-efficient maximum/minimum detection circuit for digital and video signal processing.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991
Breaking the bottleneck of sequential decoding for high-speed digital communication.
Proceedings of the 1991 International Conference on Acoustics, 1991

1990
Efficient VLSI Architectures for a High-Performance Digital Image Communication System.
IEEE J. Sel. Areas Commun., 1990


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