Hsie-Chia Chang

According to our database1, Hsie-Chia Chang authored at least 89 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2020

An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Generalized Globally-Coupled Low-Density Parity-Check Codes.
Proceedings of the IEEE Information Theory Workshop, 2018

Scalable Globally-Coupled Low-Density Parity Check Codes.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

A 188-Length Full Code Rate 333Mbps 1.08mm<sup>2</sup> Radix-4 Hybrid-Trellis Turbo Decoder with Zero Patching for 3GPP LTE-A.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Re-Polarization Processing in Extended Polar Codes.
IEICE Trans. Commun., 2017

2016
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Efficient Hardware Architecture of η<sub>T</sub> Pairing Accelerator Over Characteristic Three.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Design of LT code degree distribution with profiled output ripple size.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications.
Proceedings of the ESSCIRC Conference 2015, 2015

A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Iterative Decoding Algorithms for a Class of Non-Binary Two-Step Majority-Logic Decodable Cyclic Codes.
IEEE Trans. Commun., 2014

A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 7.11mJ/Gb/query data-driven machine learning processor (D<sup>2</sup>MLP) for big data analysis and applications.
Proceedings of the Symposium on VLSI Circuits, 2014

Iterative multi-step decoding for a class of multi-step majority-logic decodable cyclic codes.
Proceedings of the 8th International Symposium on Turbo Codes and Iterative Information Processing, 2014

Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Integrating Non-Repetitive LT Encoders With Modified Distribution to Achieve Unequal Erasure Protection.
IEEE Trans. Multim., 2013

A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis.
IEEE J. Solid State Circuits, 2013

Modified Robust Soliton Distribution (MRSD) with Improved Ripple Size for LT Codes.
IEEE Commun. Lett., 2013

An Iterative Weighted Reliability Decoding Algorithm for Two-Step Majority-Logic Decodable Cyclic Codes.
IEEE Commun. Lett., 2013

Adjusted robust Soliton distribution (ARSD) with reshaped ripple size for LT codes.
Proceedings of the International Conference on Wireless Communications and Signal Processing, 2013

Processor with side-channel attack resistance.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

An area-efficient BCH codec with echelon scheduling for NAND flash applications.
Proceedings of IEEE International Conference on Communications, 2013

2012
A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications.
IEEE J. Solid State Circuits, 2012

A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder.
IEEE J. Solid State Circuits, 2012

A low cost DPA-resistant 8-bit AES core based on ring oscillators.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

An improved LT encoding scheme with extended chain lengths.
Proceedings of the International Symposium on Information Theory and its Applications, 2012

Stochastic decoding for LDPC convolutional codes.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A fully parallel BCH codec with double error correcting capability for NOR flash applications.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

Non-repetitive encoding with increased degree-1 encoding symbols for LT codes.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.
IEEE J. Solid State Circuits, 2010

A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System.
IEEE J. Solid State Circuits, 2010

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder.
J. Low Power Electron., 2010

A multiple code-rate turbo decoder based on reciprocal dual trellis architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An improved soft BCH decoder with one extra error compensation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

A 11.5-Gbps LDPC decoder based on CP-PEG code construction.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

A 0.92mm<sup>2</sup> 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications.
IEEE J. Solid State Circuits, 2008

Multi-mode message passing switch networks applied for QC-LDPC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Structured LDPCcodes with low error floor based on PEG tanner graphs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Early-Pruned K-Best Sphere Decoding Algorithm Based on Radius Constraints.
Proceedings of IEEE International Conference on Communications, 2008

2007
Self-Compensation Technique for Simplified Belief-Propagation Algorithm.
IEEE Trans. Signal Process., 2007

Low-complexity Prediction Techniques of K-best Sphere Decoding for MIMO Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A low power turbo/Viterbi decoder for 3GPP2 applications.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Carry Estimation for Two's Complement Fixed-Width Multipliers.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A self-compensation fixed-width booth multiplier and its 128-point FFT applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Design of a power-reduction Viterbi decoder for WLAN applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004
A power and area efficient multi-mode FEC processor.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Multi-level memory systems using error control codes.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A Low-Power Design for Reed-Solomon Decoders.
J. Circuits Syst. Comput., 2003

2001
An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
New serial architecture for the Berlekamp-Massey algorithm.
IEEE Trans. Commun., 1999

1998
A (208, 192;8) Reed-Solomon decoder for DVD application.
Proceedings of the 1999 IEEE International Conference on Communications, 1998


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