Chien-Ching Lin

According to our database1, Chien-Ching Lin authored at least 12 papers between 2004 and 2010.

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Bibliography

2010
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.
IEEE J. Solid State Circuits, 2010

2009
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008
Multi-mode message passing switch networks applied for QC-LDPC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Self-Compensation Technique for Simplified Belief-Propagation Algorithm.
IEEE Trans. Signal Process., 2007

MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A low power turbo/Viterbi decoder for 3GPP2 applications.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Design of a power-reduction Viterbi decoder for WLAN applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004
A power and area efficient multi-mode FEC processor.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Multi-level memory systems using error control codes.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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