Cheng-Liang Hung

According to our database, Cheng-Liang Hung authored at least 7 papers between 2007 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes.

Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun

IEEE Trans. Circuits Syst. II Express Briefs, 2014

2012

A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology.

Bo-Qian Jiang, Cheng-Liang Hung, Bing-Hung Chen, Kuo-Hsing Cheng

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique.

Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang

IEEE J. Solid State Circuits, 2011

A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation.

Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-hao Fan, Chi-Yang Chang

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010

A 3 GHz DLL-based clock generator with stuck locking protection.

Yo-Hao Tu, Hsiang-Hao Chang, Cheng-Liang Hung, Kuo-Hsing Cheng

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2008

A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III.

Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

A Sub-1V Low-Power High-Speed Static Frequency Divider.

Kuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007