Yo-Hao Tu

According to our database1, Yo-Hao Tu authored at least 13 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2019
A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

2018
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Low supply voltage and multiphase all-digital crystal-less clock generator.
IET Circuits Devices Syst., 2018

A Wide-Range All-Digital Delay-Locked Loop for Double Data Rate Synchronous Dynamic Random Access Memory Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A body sensor node SoC for ECG/EMG applications with compressed sensing and wireless powering.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016
Proportional Static-Phase-Error Reduction for Frequency-Multiplier-Based Delay-Locked-Loop Architecture.
IEICE Trans. Electron., 2016

A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC.
IEICE Electron. Express, 2016

A chaotically injected timing technique for ring-based oscillators.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
A Synchronous Mirror Delay with Duty-Cycle Tunable Technology.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014
A low supply voltage synchronous mirror delay with quadrature phase output.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013
A low jitter delay-locked-loop applied for DDR4.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2010
A 3 GHz DLL-based clock generator with stuck locking protection.
Proceedings of the 17th IEEE International Conference on Electronics, 2010


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