Chih-Hsien Chang
According to our database1,
Chih-Hsien Chang
authored at least 22 papers
between 2003 and 2022.
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Bibliography
2022
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
2020
IEEE Trans. Circuits Syst., 2020
A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control.
IEEE J. Solid State Circuits, 2020
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply.
IEEE J. Solid State Circuits, 2018
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 0.031mm<sup>2</sup>, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A 0.034mm<sup>2</sup>, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.
IEEE J. Solid State Circuits, 2014
2012
Proceedings of the Nursing Informatics 2014 - East Meets West eSMART+, 2012
2011
A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique.
IEEE J. Solid State Circuits, 2011
2010
A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2008
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
2005
A three-dimensional registration method for automated fusion of micro PET-CT-SPECT whole-body images.
IEEE Trans. Medical Imaging, 2005
2003
Proceedings of the IEEE International Conference on Systems, 2003