Chenglong Zou

Orcid: 0000-0002-2571-3213

According to our database1, Chenglong Zou authored at least 18 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Toward a Lossless Conversion for Spiking Neural Networks with Negative-Spike Dynamics.
Adv. Intell. Syst., December, 2023

Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

2022
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor.
Microelectron. J., 2022

An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

A Full-Neuron Memory Model Designed for Neuromorphic Systems.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance.
IEICE Electron. Express, 2021

A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A Novel Conversion Method for Spiking Neural Network using Median Quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Deep Spiking Convolutional Neural Networks for Programmable Neuro-synaptic System.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
BenchBox: A User-Driven Benchmarking Framework for Fat-Client Storage Systems.
IEEE Trans. Parallel Distributed Syst., 2018

2017
COSY: An Energy-Efficient Hardware Architecture for Deep Convolutional Neural Networks Based on Systolic Array.
Proceedings of the 23rd IEEE International Conference on Parallel and Distributed Systems, 2017

A low bit-width parameter representation method for hardware-oriented convolution neural networks.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2014
Quotient Complexity of Closed Languages.
Theory Comput. Syst., 2014

2012
On orienting graphs for connectivity: Projective planes and Halin graphs.
Oper. Res. Lett., 2012


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