Ru Huang
Orcid: 0000-0001-7545-0987
According to our database1,
Ru Huang
authored at least 231 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2017, "For contributions to multi-gate silicon nanowire transistor technology".
Timeline
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On csauthors.net:
Bibliography
2024
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.
IEEE J. Solid State Circuits, March, 2024
Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip.
IEEE J. Solid State Circuits, February, 2024
A 0.39-mm<sup>2</sup> Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC.
IEEE J. Solid State Circuits, February, 2024
CoRR, 2024
CoRR, 2024
ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer.
CoRR, 2024
AttentionLego: An Open-Source Building Block For Spatially-Scalable Large Language Model Accelerator With Processing-In-Memory Technology.
CoRR, 2024
CoRR, 2024
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Sci. China Inf. Sci., October, 2023
Sci. China Inf. Sci., October, 2023
Exploring network reliability by predicting link status based on simplex neural network.
Displays, September, 2023
Neuromorphic Artificial Vision Systems Based on Reconfigurable Ion-Modulated Memtransistors.
Adv. Intell. Syst., August, 2023
Extremely-Fast, Energy-Efficient Massive MIMO Precoding With Analog RRAM Matrix Computing.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023
SIAM J. Sci. Comput., June, 2023
Experimental investigation of a novel junction-modulated hetero-layer tunnel FET with the striped gate for low power applications.
Sci. China Inf. Sci., June, 2023
A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
Equiprobability-Based Local Response Surface Method for High-Sigma Yield Estimation With Both High Accuracy and Efficiency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
Hadamard product-based in-memory computing design for floating point neural network training.
Neuromorph. Comput. Eng., March, 2023
Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
A Graph Entropy Measure From Urelement to Higher-Order Graphlets for Network Analysis.
IEEE Trans. Netw. Sci. Eng., 2023
An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
BAND-2k: Banding Artifact Noticeable Database for Banding Detection and Quality Assessment.
CoRR, 2023
CoPriv: Network/Protocol Co-Optimization for Communication-Efficient Private Inference.
CoRR, 2023
Reducing operator complexity in Algebraic Multigrid with Machine Learning Approaches.
CoRR, 2023
Regression-Oriented Knowledge Distillation for Lightweight Ship Orientation Angle Prediction with Optical Remote Sensing Images.
CoRR, 2023
HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction.
CoRR, 2023
Catching the Missing EM Consequence in Soft Breakdown Reliability in Advanced FinFETs: Impacts of Self-heating, On-State TDDB, and Layout Dependence.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
CoPriv: Network/Protocol Co-Optimization for Communication-Efficient Private Inference.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Investigation of Hot Carrier Enhanced Body Bias Effect in Advanced FinFET Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A High-Throughput and Configurable TRNG Based on Dual-Mode Memristor for Stochastic Computing.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
MPCViT: Searching for Accurate and Efficient MPC-Friendly Vision Transformer with Heterogeneous Attention.
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Memory-aware Scheduling for Complex Wired Networks with Iterative Graph Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Falcon: Accelerating Homomorphically Encrypted Convolutions for Efficient Private Mobile Network Inference.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
New Insights into Read Current Margin and Memory Window of HfO2-based Ferroelectric FET with Re-exploration of the Role of Ferroelectric Dynamics and Interface Charges during Readout.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023
A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Not your father's stochastic computing (SC)! Efficient yet Accurate End-to-End SC Accelerator Design.
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Dynamic Heterogeneous User Generated Contents-Driven Relation Assessment via Graph Representation Learning.
Sensors, 2022
Neuromorph. Comput. Eng., 2022
CoRR, 2022
Physical investigation of subthreshold swing degradation behavior in negative capacitance FET.
Sci. China Inf. Sci., 2022
Experimental investigation of the gate voltage range of negative differential capacitance in ferroelectric transistors.
Sci. China Inf. Sci., 2022
Single event transients induced by pulse laser in Ge pMOSFETs and its supply voltage dependence.
Sci. China Inf. Sci., 2022
CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA).
Sci. China Inf. Sci., 2022
In Materia Neuron Spiking Plasticity for Sequential Event Processing Based on Dual-Mode Memristor.
Adv. Intell. Syst., 2022
Artificial Multisensory Neurons with Fused Haptic and Temperature Perception for Multimodal In-Sensor Computing.
Adv. Intell. Syst., 2022
A Novel Ambipolar Ferroelectric Tunnel FinFET based Content Addressable Memory with Ultra-low Hardware Cost and High Energy Efficiency for Machine Learning.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 1.041-Mb/mm<sup>2</sup> 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Towards the Characterization of Full ID-VG Degradation in Transistors for Future Analog Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
New Insight into the Aging Induced Retention Time Degraded of Advanced DRAM Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.
IEEE J. Solid State Circuits, 2021
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network.
IEEE J. Solid State Circuits, 2021
Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array.
IEEE J. Solid State Circuits, 2021
T-GAN: A deep learning framework for prediction of temporal complex networks with adaptive graph convolution and attention mechanism.
Displays, 2021
Sci. China Inf. Sci., 2021
Sci. China Inf. Sci., 2021
12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
5.1 A 1.5μW 0.135pJ·%RH<sup>2</sup> CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A High Accuracy Multiple-Command Speech Recognition ASIC Based on Configurable One-Dimension Convolutional Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap?
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Exploration of practical teaching method of art design education based on new media technology under Internet plus background.
Proceedings of the ICISCAE 2021: 4th International Conference on Information Systems and Computer Aided Education, Dalian, China, September 24, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst., 2020
DaSGD: Squeezing SGD Parallelization Performance in Distributed Training Using Delayed Averaging.
CoRR, 2020
Sci. China Inf. Sci., 2020
High-quality and large-grain epi-like Si film by NiSi2-seed initiated lateral epitaxial crystallization (SILEC).
Sci. China Inf. Sci., 2020
Sci. China Inf. Sci., 2020
Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure.
Sci. China Inf. Sci., 2020
A photomemory by selective-assembling hybrid porphyrin-silicon nanowire field-effect transistor.
Sci. China Inf. Sci., 2020
Memristor-Based Biologically Plausible Memory Based on Discrete and Continuous Attractor Networks for Neuromorphic Systems.
Adv. Intell. Syst., 2020
Rotational Pattern Recognition by Spiking Correlated Neural Network Based on Dual-Gated MoS 2 Neuristor.
Adv. Intell. Syst., 2020
Resilient Routing Mechanism for Wireless Sensor Networks With Deep Learning Link Reliability Prediction.
IEEE Access, 2020
20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning Assisted Modeling Framework.
CoRR, 2019
Deep insight into the voltage amplification effect from ferroelectric negative capacitance.
Sci. China Inf. Sci., 2019
Sci. China Inf. Sci., 2019
Investigation of NbO<sub><i>x</i></sub>-based volatile switching device with self-rectifying characteristics.
Sci. China Inf. Sci., 2019
Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing.
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Generalized Cellular Automata Approach to Modelling Contagion and Monitoring for Emergent Events in Sensor Networks.
Proceedings of the Digital TV and Wireless Multimedia Communication, 2019
A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model.
Proceedings of the International Conference on IC Design and Technology, 2019
Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.
Proceedings of the International Conference on IC Design and Technology, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
OMI/TMI-based Modeling and Fast Simulation of Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the Handbook of Memristor Networks., 2019
2018
Numer. Linear Algebra Appl., 2018
Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits.
Microelectron. Reliab., 2018
Improvement of thermal stability of nickel germanide using nitrogen plasma pretreatment for germanium-based technology.
Sci. China Inf. Sci., 2018
GeC film with high substitutional carbon concentration formed by ion implantation and solid phase epitaxy for strained Ge n-MOSFETs.
Sci. China Inf. Sci., 2018
Integration of biocompatible organic resistive memory and photoresistor for wearable image sensing application.
Sci. China Inf. Sci., 2018
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Enhancement of HfO2 Based RRAM Performance Through Hexagonal Boron Nitride Interface Layer.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Evaluation of SRAM V<sub>min</sub> shift induced by random telegraph noise (RTN): physical understanding and prediction method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
New insights into the HCI degradation of pass-gate transistor in advanced FinFET technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Investigation on the amplitude coupling effect of random telegraph noise (RTN) in nanoscale FinFETs.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Scale-free topology optimization for software-defined wireless sensor networks: A cyber-physical system.
Int. J. Distributed Sens. Networks, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
How close to the CMOS voltage scaling limit for FinFET technology? - Near-threshold computing and stochastic computing.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
A neural network circuit with associative learning and forgetting process based on memristor neuromorphic device.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
An efficient method for solving a matrix least squares problem over a matrix inequality constraint.
Comput. Optim. Appl., 2016
Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life.
Proceedings of the International Conference on IC Design and Technology, 2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Energy-Efficient Monitoring in Software Defined Wireless Sensor Networks Using Reinforcement Learning: A Prototype.
Int. J. Distributed Sens. Networks, 2015
Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling.
Sci. China Inf. Sci., 2015
Sci. China Inf. Sci., 2015
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
Influence of selector-introduced compliance current on HfOx RRAM switching operation.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2014
Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement.
CoRR, 2014
Sci. China Inf. Sci., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A comb-gate silicon tunneling field effect transistor with improved on-state current.
Sci. China Inf. Sci., 2013
Impacts of short-channel effects on the random threshold voltage variation in nanoscale transistors.
Sci. China Inf. Sci., 2013
Sci. China Inf. Sci., 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Sci. China Inf. Sci., 2012
Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Widely reconfigurable 8<sup>th</sup>-order chebyshev analog baseband IC with proposed push-pull op-amp for Software-Defined Radio in 65nm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Microelectron. Reliab., 2011
A 0.47mW 6<sup>th</sup>-order 20MHz active filter using highly power-efficient Opamp.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Deteriorated radiation effects impact on the characteristics of MOS transistors with multi-finger configuration.
Microelectron. Reliab., 2010
IEEE J. Solid State Circuits, 2010
Proceedings of the International Conference on Machine Learning and Cybernetics, 2010
2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
Sci. China Ser. F Inf. Sci., 2008
Novel vertical channel double gate structures for high density and low power flash memory applications.
Sci. China Ser. F Inf. Sci., 2008
2003
Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET's (n-DTMOSFET) measured by gated-diode configuration.
Microelectron. Reliab., 2003
2002
Application of forward gated-diode R-G current method in extracting F-N stress-induced interface traps in SOI NMOSFETs.
Microelectron. Reliab., 2002
2001
Extraction of the lateral distribution of interface traps in MOSFETs by a novel combined gated-diode technique.
Microelectron. Reliab., 2001
Quasi-two-dimensional subthreshold current model of deep submicrometer SOI drive-in gate controlled hybrid transistors with lateral non-uniform doping profile.
Sci. China Ser. F Inf. Sci., 2001