Chenlin Shi

According to our database, Chenlin Shi authored at least 5 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A comprehensive analysis of the impact of sub 10-nm CNFET technology on 64-bit parallel prefix adders and 32-bit matrix multiply units.

Chenlin Shi, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda, Shinobu Miwa

Integr., 2026

2025

Impact of Reconvergent DFG Paths and Buffer Depth on Elastic CGRA Throughput.

Yasuto Aihara, Boma Anantasatya Adhi, Kota Aiyoshi, Chenlin Shi, Jason Anderson, Tomohiro Ueno, Kentaro Sano, Takaaki Miyajima

Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025

2024

CNFET-OCL: Open-Source Cell Libraries for Advanced CNFET Technologies.

Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda

IEEE Access, 2024

Post-Route Power Estimation: A Case Study of RIKEN-CGRA.

Chenlin Shi, Boma A. Adhi, Shinobu Miwa, Kentaro Sano

Proceedings of the IEEE International Conference on Cluster Computing, 2024

2023

CNFET7: An Open Source Cell Library for 7-nm CNFET Technology.

Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023