Tomohiro Ueno

Orcid: 0000-0002-0228-0566

According to our database1, Tomohiro Ueno authored at least 41 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A Productive HLS Simulation Approach for Multi-FPGA Systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Flexible Systolic Array Platform on Virtual 2-D Multi-FPGA Plane.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2024

2023
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster.
ACM Trans. Reconfigurable Technol. Syst., June, 2023

Streaming Hardware Compressor Generator Framework.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Hardware Specialization: Estimating Monte Carlo Cross-Section Lookup Kernel Performance and Area.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

ESSPER: Elastic and Scalable FPGA-Cluster System for High-Performance Reconfigurable Computing with Supercomputer Fugaku.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2023

2022
FPGA-Dedicated Network vs. Server Network for Pipelined Computing with Multiple FPGAs.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

Stream Computation of 3D Approximate Convex Hulls with an FPGA.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

ESSPER: Elastic and Scalable System for High-Performance Reconfigurable Computing with Software-bridged APIs.
Proceedings of the International Conference on Field-Programmable Technology, 2022

Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage.
Proceedings of the International Conference on Field-Programmable Technology, 2022

2021
Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA Cluster.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019
Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs.
IEICE Trans. Inf. Syst., 2019

Hybrid Network Utilization for Efficient Communication in a Tightly Coupled FPGA Cluster.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2018
High-productivity Programming and Optimization Framework for Stream Processing on FPGA.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Performance Analysis of Hardware-Based Numerical Data Compression on Various Data Formats.
Proceedings of the 2018 Data Compression Conference, 2018

2017
Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing.
ACM Trans. Reconfigurable Technol. Syst., 2017

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay.
IEEE J. Solid State Circuits, 2017

Design and scalability analysis of bandwidth-compressed stream computing with multiple FPGAs.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

FPGA-based Stream Computing for High-Performance N-Body Simulation using Floating-Point DSP Blocks.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017


2016
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture.
IEEE J. Solid State Circuits, 2016

A 0.0055mm<sup>2</sup> 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI.
IEICE Trans. Electron., 2016

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique.
IEEE J. Solid State Circuits, 2015

19.5 An HCI-healing 60GHz CMOS transceiver.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

An HDL-synthesized gated-edge-injection PLL with a current output DAC.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Stream Processor Generator for HPC to Embedded Applications on FPGA-based System Platform.
CoRR, 2014

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

15.1 A 0.0066mm<sup>2</sup> 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Effects of densely sampled dipole field on quantitative susceptibility mapping.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Bandwidth compression of multiple numerical data streams for high performance custom computing.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster.
SIGARCH Comput. Archit. News, 2013

Effective digitized spatial size of unit dipole field in Quantitative Susceptibility Mapping.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-Based Custom Computing.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013


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