Shinobu Miwa

According to our database, Shinobu Miwa authored at least 41 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Analyzing the Performance Impact of HPC Workloads with Gramine+SGX on 3rd Generation Xeon Scalable Processors.

Shinobu Miwa, Shin'ichiro Matsuo

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

CNFET7: An Open Source Cell Library for 7-nm CNFET Technology.

Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Analyzing Performance and Power-Efficiency Variations among NVIDIA GPUs.

Kohei Yoshida, Rio Sageyama, Shinobu Miwa, Hayato Yamaki, Hiroki Honda

Proceedings of the 51st International Conference on Parallel Processing, 2022

2021

PredCom: A Predictive Approach to Collecting Approximated Communication Traces.

Shinobu Miwa, Ignacio Laguna, Martin Schulz

IEEE Trans. Parallel Distributed Syst., 2021

2020

Footprint-Based DIMM Hotplug.

Shinobu Miwa, Masaya Ishihara, Hayato Yamaki, Hiroki Honda, Martin Schulz

IEEE Trans. Computers, 2020

RPC: An Approach for Reducing Compulsory Misses in Packet Processing Cache.

Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda

IEICE Trans. Inf. Syst., 2020

Evaluating architecture-level optimization in packet processing caches.

Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda

Comput. Networks, 2020

2019

Functionally-Predefined Kernel: a Way to Reduce CNN Computation.

Yuta Inouchi, Hayato Yamaki, Shinobu Miwa, Tomoaki Tsumura

Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

Evaluating the Impact of Energy Efficient Networks on HPC Workloads.

Giorgis Georgakoudis, Nikhil Jain, Takatsugu Ono, Koji Inoue, Shinobu Miwa, Abhinav Bhatele

Proceedings of the 26th IEEE International Conference on High Performance Computing, 2019

Multi-Level Packet Processing Caches.

Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018

Data prediction for response flows in packet processing cache.

Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda

Proceedings of the 55th Annual Design Automation Conference, 2018

2016

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip.

Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura

IEICE Trans. Inf. Syst., 2016

Evaluation of Task Mapping on Multicore Neural Network Accelerators.

Satoshi Shindo, Momoka Ohba, Tomoaki Tsumura, Shinobu Miwa

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Initial Study of Reconfigurable Neural Network Accelerators.

Momoka Ohba, Satoshi Shindo, Shinobu Miwa, Tomoaki Tsumura, Hayato Yamaki, Hiroki Honda

Proceedings of the Fourth International Symposium on Computing and Networking, 2016

2015

Profile-based power shifting in interconnection networks with on/off links.

Shinobu Miwa, Hiroshi Nakamura

Proceedings of the International Conference for High Performance Computing, 2015

Runtime multi-optimizations for energy efficient on-chip interconnections1.

Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.

Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014

Evaluation of Core Hopping on POWER7.

Shinobu Miwa, Charles Lefurgy

SIGMETRICS Perform. Evaluation Rev., 2014

Performance estimation of high performance computing systems with Energy Efficient Ethernet technology.

Shinobu Miwa, Sho Aita, Hiroshi Nakamura

Comput. Sci. Res. Dev., 2014

Area-Efficient Microarchitecture for Reinforcement of Turbo Mode.

Shinobu Miwa, Takara Inoue, Hiroshi Nakamura

IEICE Trans. Inf. Syst., 2014

Data-aware power management for periodic real-time systems with non-volatile memory.

Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu

Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Normally-off computing project: Challenges and opportunities.

Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Performance modeling for designing NoC-based multiprocessors.

Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Predict-More Router: A Low Latency NoC Router with More Route Predictions.

Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Integrating Multi-GPU Execution in an OpenACC Compiler.

Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Naoya Maruyama

Proceedings of the 42nd International Conference on Parallel Processing, 2013

Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping.

Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.

Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the Design, Automation and Test in Europe, 2013

McRouter: Multicast within a router for high performance network-on-chips.

Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012

Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches.

Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating.

Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Communication Library to Overlap Computation and Communication for OpenCL Application.

Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Stepwise sleep depth control for run-time leakage power saving.

Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

A novel power-gating scheme utilizing data retentiveness on caches.

Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth.

Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita

J. Comput. Sci. Technol., 2011

Evaluation of GPU-Based Empirical Mode Decomposition for Off-Line Analysis.

Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo

IEICE Trans. Inf. Syst., 2011

2010

Parallelizing Hilbert-Huang Transform on a GPU.

Pulung Waskito, Shinobu Miwa, Yasue Mitsukura, Hironori Nakajo

Proceedings of the First International Conference on Networking and Computing, 2010

An Effective Replacement Policy Focusing on Lifetime of a Cache Line.

Hiroki Yokoyama, Yuhei Horibe, Peng Zhang, Shinobu Miwa, Hironori Nakajo

Proceedings of the 2010 International Conference on Computer Design, 2010

2009

Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor.

Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo

Proceedings of the 2009 International Conference on Computer Design, 2009

2008

A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases.

Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita

IEICE Trans. Inf. Syst., 2008

Low-Complexity Bypass Network Using Small RAM.

Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita

Proceedings of the 2008 International Conference on Computer Design, 2008

2007

Optimal pipeline depth with pipeline stage unification adoption.

Jun Yao, Shinobu Miwa, Hajime Shimada, Shinji Tomita

SIGARCH Comput. Archit. News, 2007