Ryota Shioya

According to our database, Ryota Shioya authored at least 44 papers between 2006 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Principal Factor of Performance in Decoupled Front-End.

Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai

IEICE Trans. Inf. Syst., December, 2023

Collecting Cyclic Garbage across Foreign Function Interfaces: Who Takes the Last Piece of Cake?

Tetsuro Yamazaki, Tomoki Nakamaru, Ryota Shioya, Tomoharu Ugawa, Shigeru Chiba

Proc. ACM Program. Lang., 2023

PEZY-SC3: A MIMD Many-core Processor for Energy-efficient Computing.

Naoya Hatta, Shuntaro Tsunoda, Kouhei Uchida, Taichi Ishitani, Ryota Shioya, Kei Ishii

CoRR, 2023

Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors.

Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS.

Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs.

Yuichi Sugiyama, Reoma Matsuo, Ryota Shioya

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA.

Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Out-of-Step Pipeline for Gather/Scatter Instructions.

Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Sound and Complete Algorithm for Code Generation in Distance-Based ISA.

Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction, 2023

CNFET7: An Open Source Cell Library for 7-nm CNFET Technology.

Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison.

Yasutaka Matsuda, Ryota Shioya, Hideki Ando

IEICE Trans. Inf. Syst., 2022

T-SKID: Predicting When to Prefetch Separately from Address Prediction.

Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout.

Soramichi Akiyama, Ryota Shioya

Proceedings of the ICPE '21: ACM/SPEC International Conference on Performance Engineering, 2021

Accurate and Fast Performance Modeling of Processors with Decoupled Front-end.

Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Compiling and Optimizing Real-world Programs for STRAIGHT ISA.

Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core.

Susumu Mashimo, Ryota Shioya, Koji Inoue

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2020

A High-Performance Out-of-Order Soft Processor Without Register Renaming.

Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline.

Reoma Matsuo, Ryota Shioya, Hideki Ando

IEEE Comput. Archit. Lett., 2019

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.

Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

Bank-Aware Instruction Scheduler for a Multibanked Register File.

Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

J. Inf. Process., 2018

Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications.

Keita Doi, Ryota Shioya, Hideki Ando

J. Inf. Process., 2018

VMOR: Microarchitectural Support for Operand Access in an Interpreter.

Susumu Mashimo, Ryota Shioya, Koji Inoue

IEEE Comput. Archit. Lett., 2018

STRAIGHT: Hazardless Processor Architecture Without Register Renaming.

Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai

Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Isolation-Safe Speculative Access Control for Hardware Transactional Memory.

Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

An Analysis and a Solution of False Conflicts for Hardware Transactional Memory.

Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Rearranging Random Issue Queue with High IPC and Short Delay.

Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Application of Timing Fault Detection to Rocket Core on FPGA.

Ushio Jimbo, Ryota Shioya, Masahiro Goshima

Proceedings of the Sixth International Symposium on Computing and Networking, 2018

An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming.

Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai

Proceedings of the International Conference on Field-Programmable Technology, 2018

A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode.

Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando

Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency.

Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Inf. Syst., 2017

Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology.

Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Electron., 2017

Applying Razor Flip-Flops to SRAM Read Circuits.

Ushio Jimbo, Junji Yamada, Ryota Shioya, Masahiro Goshima

IEICE Trans. Electron., 2017

Initial study of a phase-aware scheduling for hardware transactional memory.

Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura

Proceedings of the IEEE Pacific Rim Conference on Communications, 2017

2016

FXA: Executing Instructions in Front-End for Energy Efficiency.

Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando

IEICE Trans. Inf. Syst., 2016

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency.

Ryota Shioya, Hideki Ando

IEICE Trans. Inf. Syst., 2016

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control.

Hideki Ando, Ryota Shioya

IEICE Trans. Inf. Syst., 2016

2015

Address Order Violation Detection with Parallel Counting Bloom Filters.

Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Electron., 2015

2014

A Front-End Execution Architecture for High Energy Efficiency.

Ryota Shioya, Masahiro Goshima, Hideki Ando

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Energy efficiency improvement of renamed trace cache through the reduction of dependent path length.

Ryota Shioya, Hideki Ando

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Register Indirect Jump Target Forwarding.

Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Inf. Syst., 2013

2011

Low-Overhead Architecture for Security Tag.

Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai

IEICE Trans. Inf. Syst., 2011

2010

Register Cache System Not for Latency Reduction Purpose.

Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai

Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2009

String-Wise Information Flow Tracking against Script Injection Attacks.

Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

2006

Base Address Recognition with Data Flow Tracking for Injection Attack Detection.

Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai

Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006