Chenyang Lv
Orcid: 0009-0007-4500-8961
According to our database1,
Chenyang Lv
authored at least 15 papers
between 2016 and 2025.
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Bibliography
2025
A Recursive Partition-Based In-Memory SIMD Computation Scheduler for Memory Footprint Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2025
IEEE Internet Things J., January, 2025
HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers.
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2024
IEEE Trans. Computers, October, 2024
High-Quality Iterative Logic Compiler for In-Memory SIMD Computation with Tight Coupling of Synthesis and Scheduling.
CoRR, 2024
Integrating Social Value Orientation and Motion Safety Controller in Autonomous Driving: Improving the Safety of Unprotected Left-Turn Behaviour.
Proceedings of the 27th IEEE International Conference on Intelligent Transportation Systems, 2024
2023
GPT-LS: Generative Pre-Trained Transformer with Offline Reinforcement Learning for Logic Synthesis.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
XMG-GPPIC: Efficient and Robust General-Purpose Processing-in-Cache with XOR-Majority-Graph.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the 2023 7th International Conference on Electronic Information Technology and Computer Engineering, 2023
2022
Proceedings of the International Conference on Networking and Network Applications, 2022
Proceedings of the Mobile Networks and Management - 12th EAI International Conference, 2022
Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
2019
2018
2016
A local dynamic method for tracking communities and their evolution in dynamic networks.
Knowl. Based Syst., 2016