Chi-Heng Yang

According to our database, Chi-Heng Yang authored at least 8 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Large Language Models for Conducting Advanced Text Analytics Information Systems Research.

Benjamin M. Ampel, Chi-Heng Yang, James Lee Hu, Hsinchun Chen

CoRR, 2023

2022

Human vs machine: Do customer service chatbots perform better?

Chi-Heng Yang, Ju-Chun Yen, Tawei David Wang

Proceedings of the 26th Pacific Asia Conference on Information Systems, 2022

2017

3X endurance enhancement by advanced signal processor for 3D NAND flash memory.

Wei Lin, Yu-Cheng Hsu, Tsai-Hao Kuo, Yu-Siang Yang, Szu-Wei Chen, Chun-Wei Tsao, An-Chang Liu, Lih-Yuarn Ou, Tien-Ching Wang, Shao-Wei Yen, Yu-Hsiang Lin, Kuo-Hsin Lai, Chi-Heng Yang, Li-Chun Liang, Pei-Jung Hsu

Proceedings of the 2017 IEEE Information Theory Workshop, 2017

2015

An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability.

Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee

IEEE Trans. Very Large Scale Integr. Syst., 2015

2013

An area-efficient BCH codec with echelon scheduling for NAND flash applications.

Chi-Heng Yang, Yi-Hsun Chen, Hsie-Chia Chang

Proceedings of IEEE International Conference on Communications, 2013

2012

A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories.

Yi-Hsun Chen, Chi-Heng Yang, Hsie-Chia Chang

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A fully parallel BCH codec with double error correcting capability for NOR flash applications.

Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, Hsie-Chia Chang

Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011

A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices.

Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee

IEEE Trans. Circuits Syst. II Express Briefs, 2011