Yi-Min Lin

According to our database1, Yi-Min Lin authored at least 10 papers between 2008 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2015
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability.
IEEE Trans. VLSI Syst., 2015

2014
A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems.
IEEE Trans. on Circuits and Systems, 2014

2013
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation.
IEEE Trans. VLSI Syst., 2013

2012
A fully parallel BCH codec with double error correcting capability for NOR flash applications.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices.
IEEE Trans. on Circuits and Systems, 2011

A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systems.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System.
J. Solid-State Circuits, 2010

A hybrid forecast marketing timing model based on probabilistic neural network, rough set and C4.5.
Expert Syst. Appl., 2010

An improved soft BCH decoder with one extra error compensation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2008
Deconstructing mobile commerce service with continuance intention.
IJMC, 2008


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