Chin-Cheng Kuo

According to our database, Chin-Cheng Kuo authored at least 10 papers between 2005 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

A fast heuristic approach for parametric yield enhancement of analog designs.

Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo, I-Ching Tsai

ACM Trans. Design Autom. Electr. Syst., 2012

Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits.

Chin-Cheng Kuo, Wei-Yi Hu, Yi-Hung Chen, Jui-Feng Kuan, Yi-Kan Cheng

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010

Fast and Accurate Analysis of Supply Noise Effects in PLL With Noise Interactions.

Chin-Cheng Kuo, Chien-Nan Jimmy Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Behavior-level yield enhancement approach for large-scaled analog circuits.

Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu

Proceedings of the 47th Design Automation Conference, 2010

2009

Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models.

Chin-Cheng Kuo, Meng-Jung Lee, Chien-Nan Jimmy Liu, Ching-Ji Huang

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application.

Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo

IEICE Trans. Electron., 2009

A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level.

Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2006

An Efficient Approach to Build Accurate Behavioral Models of PLL Designs.

Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems.

Chin-Cheng Kuo, Chien-Nan Jimmy Liu

Proceedings of the IFIP VLSI-SoC 2006, 2006

2005

An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs.

Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005