Yen-Lung Chen

According to our database1, Yen-Lung Chen authored at least 19 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping.
IEEE Trans. Biomed. Circuits Syst., December, 2023

A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021
A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome.
IEEE Trans. Parallel Distributed Syst., 2021

A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing.
IEEE J. Solid State Circuits, 2021

A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2016
Wave digital filter based analog circuit emulation on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Layout-aware analog synthesis environment with yield consideration.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Simultaneous optimization for low dropout regulator and its error amplifier with process variation.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Robust guidance law design for UAVs.
Proceedings of the 11th IEEE International Conference on Control & Automation, 2014

REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
A layout-aware automatic sizing approach for retargeting analog integrated circuits.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

LASER: layout-aware analog synthesis environment on laker.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A fast heuristic approach for parametric yield enhancement of analog designs.
ACM Trans. Design Autom. Electr. Syst., 2012

2010
Behavior-level yield enhancement approach for large-scaled analog circuits.
Proceedings of the 47th Design Automation Conference, 2010


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