Chin Yang Koay

According to our database, Chin Yang Koay authored at least 4 papers between 2016 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS.

Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ping-Chuan Chiang, Ken Chang

IEEE J. Solid State Circuits, 2017

An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only).

Wei Ting Loke, Chin Yang Koay

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

Energy-aware scheduling for task adaptive FPGAs.

Wei Ting Loke, Chin Yang Koay

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS.

Kok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ken Chang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016