Ping-Chuan Chiang

According to our database1, Ping-Chuan Chiang authored at least 11 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET.
IEEE J. Solid State Circuits, 2020

2019
A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A 112-GB/S PAM4 Transmitter in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS.
IEEE J. Solid State Circuits, 2017

2015
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies.
IEEE J. Solid State Circuits, 2015

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
100Gb/s ethernet chipsets in 65nm CMOS technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension.
Proceedings of the International SoC Design Conference, 2011


  Loading...