Siok-Wei Lim

Orcid: 0000-0001-8843-7175

According to our database1, Siok-Wei Lim authored at least 7 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019

2018
A 112-GB/S PAM4 Transmitter in 16NM FinFET.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS.
IEEE J. Solid State Circuits, 2017

2016
A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
3.3 A 0.5-to-32.75Gb/s flexible-reach wireline transceiver in 20nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs.
IEEE J. Solid State Circuits, 2013


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