Chin-Yang Lo

According to our database, Chin-Yang Lo authored at least 3 papers between 2019 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks.

Po-Tsang Huang, I-Chen Wu, Chin-Yang Lo, Wei Hwang

IEEE Open J. Circuits Syst., 2021

2020

Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs.

Chin-Yang Lo, Po-Tsang Huang, Wei Hwang

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019

An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network.

I-Chen Wu, Po-Tsang Huang, Chin-Yang Lo, Wei Hwang

Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019