Po-Tsang Huang

According to our database1, Po-Tsang Huang authored at least 69 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Reshaping System Design in 3D Integration: Perspectives and Challenges.
Proceedings of the 2023 International Symposium on Physical Design, 2023

2022
Digi-FH-OFDM: An all-digital wideband frequency-hopped OFDM system.
Phys. Commun., 2022

Variation Aware Training of Hybrid Precision Neural Networks with 28nm HKMG FeFET Based Synaptic Core.
CoRR, 2022

An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Cognitive Bus Coding Scheme for Inter-Chip Communications of Deep Learning Accelerator Chiplet on Low-cost Si and Glass Interposer.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM.
Proceedings of the 19th International SoC Design Conference, 2022

Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator.
Proceedings of the 19th International SoC Design Conference, 2022

Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications.
Proceedings of the International Conference on IC Design and Technology, 2022

Design Exploration of An Energy-Efficient Acceleration System for CNNs on Low-Cost Resource-Constraint SoC-FPGAs.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Rotational motion-aware beam refinement for high-throughput mmWave communications.
Wirel. Networks, 2021

Design and Implementation for Deep Learning Based Adjustable Beamforming Training for Millimeter Wave Communication Systems.
IEEE Trans. Veh. Technol., 2021

Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks.
IEEE Open J. Circuits Syst., 2021

An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks.
Proceedings of the 18th International SoC Design Conference, 2021

Ultra Low Power 3D-Embedded Convolutional Neural Network Cube Based on α-IGZO Nanosheet and Bi-Layer Resistive Memory.
Proceedings of the International Conference on IC Design and Technology, 2021

2020
3D On-Demand Flying Mobile Communication for Millimeter-Wave Heterogeneous Networks.
IEEE Netw., 2020

Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
Built-In Self-Test/Repair Methodology for Multiband RF-Interconnected TSV 3D Integration.
IEEE Des. Test, 2019

28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes.
IEEE Trans. Biomed. Circuits Syst., 2017

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection.
IEEE J. Solid State Circuits, 2017

An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

The SMEM Seeding Acceleration for DNA Sequence Alignment.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications.
Proceedings of the VLSI Design, Automation and Test, 2015

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction.
Proceedings of the VLSI Design, Automation and Test, 2015

Energy-efficient gas recognition system with event-driven power control.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications.
IEEE Trans. Biomed. Circuits Syst., 2014

Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Energy-efficient configurable discrete wavelet transform for neural sensing applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Through-silicon-via-based double-side integrated microsystem for neural sensing applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012
Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks.
J. Electr. Comput. Eng., 2012

A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

On-chip self-calibrated process-temperature sensor for TSV 3D integration.
Proceedings of the IEEE 25th International SOC Conference, 2012

Substrate noise suppression technique for power integrity of TSV 3D integration.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables.
IEEE J. Solid State Circuits, 2011

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

On-demand memory sub-system for multi-core SoCs.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder.
J. Low Power Electron., 2010

Power noise suppression technique using active decoupling capacitor for TSV 3D integration.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A decision support system of statistical process control for printed circuit boards manufacturing.
Proceedings of the International Conference on Machine Learning and Cybernetics, 2010

2009
An adaptive congestion-aware routing algorithm for mesh network-on-chip platform.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

"Green" micro-architecture and circuit co-design for ternary content addressable memory.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A 65nm low power 2T1D embedded DRAM with leakage current reduction.
Proceedings of the 2007 IEEE International SOC Conference, 2007

2006
2-level FIFO architecture design for switch fabrics in network-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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