Devleena Ghosh

Orcid: 0000-0002-1110-1259

According to our database1, Devleena Ghosh authored at least 6 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
Harnessing Multiple BMC Engines Together for Efficient Formal Verification.
Proceedings of the 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2023

2022
Clustering Based Parameter Estimation of Thyroid Hormone Pathway.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022

2021
Automatic Generation of Route Control Chart From Validated Signal Interlocking Plan.
IEEE Trans. Intell. Transp. Syst., 2021

2015
Aiding Teaching of Logic Design and Computer Organization through Dynamic Problem Generation and Automatic Checker Using COLDVL Tool.
Proceedings of the Seventh IEEE International Conference on Technology for Education, 2015

A Virtual Laboratory Package to Support Teaching of Logic Design and Computer Organization.
Proceedings of the Seventh IEEE International Conference on Technology for Education, 2015

Layout Validation Using Graph Grammar and Generation of Yard Specific Safety Properties for Railway Interlocking Verification.
Proceedings of the 2015 Asia-Pacific Software Engineering Conference, 2015


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