Deog-Kyoon Jeong

According to our database1, Deog-Kyoon Jeong authored at least 138 papers between 1993 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2017, "For development of Digital Video Interface and High Definition Multimedia Interface standards".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage.
IEEE J. Solid State Circuits, 2020

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference.
IEEE J. Solid State Circuits, 2020

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

32.4 A 0.4-to-1.2V 0.0057mm<sup>2</sup> 55fs-Transient-FoM Ring-Amplifier-Based Low-Dropout Regulator with Replica-Based PSR Enhancement.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm<sup>2</sup> Current Density.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

18.6 A 92.8%-Peak-Efficiency 60A 48V-to-1V 3-Level Half-Bridge DC-DC Converter with Balanced Voltage on a Flying Capacitor.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A<sup>3</sup>: Accelerating Attention Mechanisms in Neural Networks with Approximation.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
A Modulo-FIR Equalizer for Wireline Communications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Noise-Immunity-Enhanced Analog Front-End for $36\times64$ Touch-Screen Controllers With 20- $\text{V}_{\text{PP}}$ Noise Tolerance at 100 kHz.
IEEE J. Solid State Circuits, 2019

A Mutual Capacitance Touch Readout IC With 64% Reduced-Power Adiabatic Driving Over Heavily Coupled Touch Screen.
IEEE J. Solid State Circuits, 2019

A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology.
IEEE J. Solid State Circuits, 2019

A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors.
IEEE Access, 2019

Reference Spur Reduction Techniques for a Phase-Locked Loop.
IEEE Access, 2019

A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 370-fJ/b, 0.0056 mm<sup>2</sup>/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm<sup>2</sup> Controller and 80ns Recovery Time.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Compact Self-Capacitance Sensing Analog Front-End for a Touch Detection in Low-Power Mode.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

An Always-On 0.53-to-13.4 mW Power-Scalable Touchscreen Controller for Ultrathin Touchscreen Displays With Current-Mode Filter and Incremental Hybrid ΔΣ ADC.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A $4.7\mu \mathrm{A}$ Quiescent Current Synthesizable Digital Low Dropout Regulator in 28-nm CMOS.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS.
Proceedings of the International Conference on Electronics, Information, and Communication, 2019

A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards.
IEEE Trans. Ind. Electron., 2018

A 2.44-pJ/b 1.62-10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 20 k-to-100kS/s Sub-µW 9.5b-ENOB Asynchronous SAR ADC for Energy-Harvesting Body Sensor Node SoCs in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 35-Gb/s 0.65-pJ/b Asymmetric Push-Pull Inverter-Based VCSEL Driver With Series Inductive Peaking in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

4-Channel Push-Pull VCSEL Drivers for HDMI Active Optical Cable in 0.18-μm CMOS.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Adiabatically driven touch controller analog front-end for ultra-thin displays.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

A 10-Gb/s, 0.03-mm<sup>2</sup>, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 0.4-to-1 V Voltage Scalable ΔΣ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G<sub>m</sub>-Regulated Resistive-Feedback Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 0.015-mm<sup>2</sup> Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.
Sensors, 2017

Introduction to the Special Section on the 2016 Asian Solid-State Circuits Conference (A-SSCC 2016).
IEEE J. Solid State Circuits, 2017

29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A compact 87.1-dB DR bandwidth-scalable delta-sigma modulator based on dynamic gain-bandwidth-boosting inverter for audio applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2016

20-Gb/s 5-V<sub>PP</sub> and 25-Gb/s 3.8-V<sub>PP</sub> Area-Efficient Modulator Drivers in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 0.36 pJ/bit, 0.025 mm<sup>2</sup>, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G<sub>m</sub> Bias.
IEEE J. Solid State Circuits, 2016

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016

11.6 A 100-TRX-channel configurable 85-to-385Hz-frame-rate analog front-end for touch controller with highly enhanced noise immunity of 20Vpp.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A theoretical analysis of phase shift in pulse injection-locked oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process.
IEEE J. Solid State Circuits, 2015

A power-efficient 600-mV<sub>pp</sub> voltage-mode driver with independently matched pull-up and pull-down impedances.
Int. J. Circuit Theory Appl., 2015

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation.
Proceedings of the Symposium on VLSI Circuits, 2015

20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A low-power pulse position modulation transceiver.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
Proceedings of the ESSCIRC Conference 2015, 2015

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2014

1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels.
IEEE J. Solid State Circuits, 2014

Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator.
IEEE J. Solid State Circuits, 2014

A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.
Proceedings of the ESSCIRC 2014, 2014

A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth.
Proceedings of the International Conference on Electronics, Information and Communications, 2014

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM.
IEEE J. Solid State Circuits, 2013

A 0.032mm<sup>2</sup> 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology.
Proceedings of the International SoC Design Conference, 2012

Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface.
Proceedings of the International SoC Design Conference, 2012

A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low-noise differential front-end and its controller for capacitive touch screen panels.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Multidrop Bus Design Scheme With Resistor-Based Impedance Matching on Nonuniform Impedance Lines.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control.
IEEE J. Solid State Circuits, 2011

250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS.
IEEE J. Solid State Circuits, 2011

A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems.
IEEE Trans. Instrum. Meas., 2010

A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller.
IEEE J. Solid State Circuits, 2010

A clock synchronization system with IEEE 1588-2008 adapters over existing Gigabit Ethernet equipment.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
High-speed 10-bit LCD column driver with a split DAC and a class-AB output buffer.
IEEE Trans. Consumer Electron., 2009

Design Optimization of On-Chip Inductive Peaking Structures for 0.13-μm CMOS 40-Gb/s Transmitter Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A Fully Integrated 0.13-µm CMOS 40-Gb/s Serial Link Transceiver.
IEEE J. Solid State Circuits, 2009

Practical considerations in the design and implementation of time synchronization systems using IEEE 1588.
IEEE Commun. Mag., 2009

A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008
Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

An ethernet switch architecture for bandwidth provision of broadband access networks.
IEEE Commun. Mag., 2008

Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture.
IEEE J. Solid State Circuits, 2007

A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme.
IEEE J. Solid State Circuits, 2007

Virtual minimum potential queuing.
J. High Speed Networks, 2007

Enhanced token bucket policer using reduced fair queuing for Ethernet access networks.
IET Commun., 2007

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µm.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A single-chip storage LSI for home networks.
IEEE Commun. Mag., 2005

2003
Multi-gigabit-rate clock and data recovery based on blind oversampling.
IEEE Commun. Mag., 2003

1998
Design and Implementation of OTCA MAC Protocol for High-Speed Point-to-Point Ring Network.
Proceedings of the Proceedings 23rd Conference on Local Computer Networks, 1998

1995
U-Cache: A Cost-Effective Solution to the Synonym Problem.
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

1994
A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Hotpads - macro-dells for gigabit I/O.
Proceedings of the Hot Interconnects II, 1994

1993
V-P cache: a storage efficient virtual cache organization.
Microprocess. Microsystems, 1993

Threaded prefetching: An adaptive instruction prefetch mechanism.
Microprocess. Microprogramming, 1993


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