Chongxiao Li

According to our database, Chongxiao Li authored at least 9 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity.

Pengwei Jin, Zhe Fan, Yongwei Zhao, Zidong Du, Hongrui Guo, Ziyuan Nan, Yifan Hao, Chongxiao Li, Tianyun Ma, Zhenxing Zhang, Xiaqing Li, Wei Li, Xing Hu, Qi Guo, Zhiwei Xu, Tianshi Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2025

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation.

Yang Zhang, Rui Zhang, Jiaming Guo, Lei Huang, Di Huang, Yunpu Zhao, Shuyao Cheng, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Qi Guo, Yunji Chen

CoRR, October, 2025

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs.

Pengwei Jin, Di Huang, Chongxiao Li, Shuyao Cheng, Yang Zhao, Xinyao Zheng, Jiaguo Zhu, Shuyi Xing, Bohan Dou, Rui Zhang, Zidong Du, Qi Guo, Xing Hu

CoRR, July, 2025

CodeV-R1: Reasoning-Enhanced Verilog Generation.

Yaoyu Zhu, Di Huang, Han-Qi Lyu, Xiaoyun Zhang, Chongxiao Li, Wenxuan Shi, Yutong Wu, Jianan Mu, Jinghua Wang, Yang Zhao, Pengwei Jin, Shuyao Cheng, Shengwen Liang, Xishan Zhang, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen

CoRR, May, 2025

QiMeng-CPU-v2: Automated Superscalar Processor Design by Learning Data Dependencies.

Shuyao Cheng, Rui Zhang, Wenkai He, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yifan Hao, Guanglin Xu, Yuanbo Wen, Ling Li, Qi Guo, Yunji Chen

CoRR, May, 2025

Automated Superscalar Processor Design by Learning Data Dependencies.

Shuyao Cheng, Rui Zhang, Wenkai He, Pengwei Jin, Chongxiao Li, Zidong Du, Xing Hu, Yifan Hao, Guanglin Xu, Yuanbo Wen, Ling Li, Qi Guo, Yunji Chen

Proceedings of the Thirty-Fourth International Joint Conference on Artificial Intelligence, 2025

2024

AGON: Automated Design Framework for Customizing Processors from ISA Documents.

Chongxiao Li, Di Huang, Pengwei Jin, Tianyun Ma, Husheng Han, Shuyao Cheng, Yifan Hao, Yongwei Zhao, Guanglin Xu, Zidong Du, Rui Zhang, Xiaqing Li, Yuanbo Wen, Yanjun Wu, Chen Zhao, Xing Hu, Qi Guo

CoRR, 2024

CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization.

Yang Zhao, Di Huang, Chongxiao Li, Pengwei Jin, Ziyuan Nan, TianYun Ma, Lei Qi, Yansong Pan, Zhenxing Zhang, Rui Zhang, Xishan Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen

CoRR, 2024

Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation.

Shuyao Cheng, Chongxiao Li, Zidong Du, Rui Zhang, Xing Hu, Xiaqing Li, Guanglin Xu, Yuanbo Wen, Qi Guo

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024